kadhiem_ayob wrote:
> I am trying to simulate in Modelsim XE web edition a verilog only project
> consisting of top level and few components. All components have same time
> resolution units and have wire type outputs. The problem is that Modelsim
> doesn't recognise the drive of any component's output connected to
> another's input. Yet it accepts the drive when connected to an output at
> toplevel itself.

http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_body.html#8.0%20Module%20Instances

I am trying to simulate in Modelsim XE web edition a verilog only project
consisting of top level and few components. All components have same time
resolution units and have wire type outputs. The problem is that Modelsim
doesn't recognise the drive of any component's output connected to
another's input. Yet it accepts the drive when connected to an output at
toplevel itself.
What am I missing here? Is there anything else to do about binding?
Any help appreciated. This problem does not occur with vhdl projects.

kadhiem
	   
					
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