> I'd like to implement an SPI master to read an AD7924 ADC. The thing is
> that there are some setup and hold time I have to respect, ie CS'to SCLK
> setup time, SCLK to DOUT valid hold time, etc. They go from typically 10 ns
> to 50 ns.
>
> What's the best way to implement these delays?
If the FPGA is too fast, add some dummy states to your state machine where
you don't change the outputs.
Reply by Marc Jet●October 20, 20092009-10-20
> What's the best way to implement these delays?
You can easily implement them with a state machine that is clocked
considerably faster than the SPI bit rate.
Reply by ElVale●October 20, 20092009-10-20
>I'd like to implement an SPI master to read an AD7924 ADC. The thing is
>that there are some setup and hold time I have to respect, ie CS'to SCLK
>setup time, SCLK to DOUT valid hold time, etc. They go from typically 10
ns
>to 50 ns.
>
>What's the best way to implement these delays?
>
>
>
I mean implementing them in VHDL.
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Reply by ElVale●October 20, 20092009-10-20
I'd like to implement an SPI master to read an AD7924 ADC. The thing is
that there are some setup and hold time I have to respect, ie CS'to SCLK
setup time, SCLK to DOUT valid hold time, etc. They go from typically 10 ns
to 50 ns.
What's the best way to implement these delays?