On Nov 12, 11:20=A0am, Didi <d...@tgi-sci.com> wrote:
>
> That is true, it does seem to work. On the 6.3 version, at least.
> The end result I get does go through that conversion as well, I
> can see that during compilation, the vhdl source is also visible
> I think.
>
> What does seem not to work in the 11 thing is some higher level
> automation, they don't bother parsing the Abel source for pin
> assignments and endup without any (my assumption only, could
> be anything else).

By default I think it auto-fits (floats the pins), but if you click
Lock Pins, you get a .UCF for that fit pass, and can then move the
pins about in that file.

Usually I let the fitter have first pass, and create the reports etc,
and then I start worrying about the pins.
It's also good to get design thru the hoops once, before starting to
nail things down..

Not extracting that info from ABEL is rather lazy of Xilinx - that's
really intern level stuff, perhaps they don't sell that many PLDs into
long design life projects ?
Still, a generated UCF file looks simple enough..
-jg

On Nov 12, 11:31=A0am, Gabor <ga...@alacron.com> wrote:
> I don't think Xilinx ever
> had a version that would allow top-level code in Abel,
> but I could be wrong on that because most of my designs
> are FPGA based rather than CPLD where top-level Abel
> would make sense. =A0

The ABEL examples I have here, do not need to have SCH top levels.
( I think one does, to show how it can be done..)
-jg

On Nov 11, 4:59=A0pm, -jg <jim.granvi...@gmail.com> wrote:
> On Nov 12, 10:41=A0am, Didi <d...@tgi-sci.com> wrote:> On Nov 11, 11:13=
=A0am, -jg <jim.granvi...@gmail.com> wrote:
>
> > > ....
> > > I've sent Dimiter a disk image of an .ABL project compiled into a
> > > XCR3128, so he can check what has changed....
>
> > While having my morning coffee at 11 PM (still half full) I tried
> > the newest version I have here (ISE11) on my test project, the one
> > with the one toggling bit shifting through another five.
> > I got a warning that the project would be converted to a new
> > format not usable by older versions; and a promise the old
> > version would be zipped somewhere (yet to check that, but I
> > have the source on my DPS disk beyond any alien access anyway).
> > The the project got open, but the Abel source was gone; the
> > top source now was its translation to vhdl.
>
> =A0Fair enough, I thought,
>
> > I was warned for that sort of thing.
>
> Err No. I'd say NOT fair-enough.
> WHY should they need to replace YOUR source code ?
>
> If they have Abel-to-VHDL working, then simply run that in the
> background.
>
> I was told by a friend a couple of years back, that was how Xilinx
> handled his abel - it did VHDL spins, but they were 'hidden', and it
> took Xilinx a few months to knock the edges off that change, but it
> DID sound like it all worked.
>
> > What I was not warned of
> > was the fact that it would no longer work... It just won't
> > compile, I think it does not preserve the pin numbers I
> > have assigned in the Abel file.
> > I suppose it can be tweaked to eventually work, if there
> > were any sane reason why someone would want to do that.
> > I don't, that's sure :-).
> > But I was reminded once more why it is so important
> > to have all design tools under control, the coolrunner
> > series is the finest programmable silicon I have seen and
> > I clearly will have to adapt my lc to the 3 and perhaps
> > 2 series, hopefully they will live for another while.
>
> =A0Have you looked at the Atmel ATF1508RE ?
> I use the CUPL tool flows on their ATF15xx family.
> =A0It compiles in a fraction of a second, has a stable, flash-Drivable
> image and it can create test vector files.
> =A0Hooked to a button in my favourite text editor.
> Simple.Stable.Bulletproof (well, almost: Zero Angst)
>
> -jg

I would not consider ISE 11 for anything but the very latest
FPGA's.  ISE 6.3 is probably the most stable version and if
your device is included, you should use it.

I have to admit that I use Verilog almost exclusively for
projects since moving away from Foundation 4.1 (the
Aldec-based one) which had decent schematics.  I still
have that version running to support old projects, but
I think it may predate the Coolrunner II.  In any case
that version certainly had Abel and I used it.  It also
had serious bugs including an inability to deal with
paths that are not 8.3 all the way up from the root
and a necessity to have the execution path point to
the Abel compiler even when running from the GUI.  The
usual symptom if your file name was longer than 8 characters
was to fail with no explanation given.

Xilinx has already decided to orphan some older FPGA
products with ISE 11.  ISE 10.1.03i is the last version
to support the older parts.  It is also fairly stable
and you can get the webpack version with a little bit
of browsing (older versions are referred to as "classic").

In any case the GUI for newer tool versions seems to
get less intuitive and more clunky with each version,
as you have no doubt seen.  I don't think Xilinx ever
had a version that would allow top-level code in Abel,
but I could be wrong on that because most of my designs
are FPGA based rather than CPLD where top-level Abel
would make sense.  If you need to do anything serious
with Coolrunner I'd suggest moving to VHDL or Verilog
just to avoid the crappy schematic editor.

Oh for the days of PALASM...

Regards,
Gabor

On Nov 11, 11:59=A0pm, -jg <jim.granvi...@gmail.com> wrote:
> ...
> I was told by a friend a couple of years back, that was how Xilinx
> handled his abel - it did VHDL spins, but they were 'hidden', and it
> took Xilinx a few months to knock the edges off that change, but it
> DID sound like it all worked.

That is true, it does seem to work. On the 6.3 version, at least.
The end result I get does go through that conversion as well, I
can see that during compilation, the vhdl source is also visible
I think.

What does seem not to work in the 11 thing is some higher level
automation, they don't bother parsing the Abel source for pin
assignments and endup without any (my assumption only, could
be anything else).

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/

Original message: http://groups.google.com/group/comp.arch.embedded/msg/bc9=
607aec82349d8?dmode=3Dsource

On Nov 12, 10:41=A0am, Didi <d...@tgi-sci.com> wrote:
> On Nov 11, 11:13=A0am, -jg <jim.granvi...@gmail.com> wrote:
>
> > ....
> > I've sent Dimiter a disk image of an .ABL project compiled into a
> > XCR3128, so he can check what has changed....
>
> While having my morning coffee at 11 PM (still half full) I tried
> the newest version I have here (ISE11) on my test project, the one
> with the one toggling bit shifting through another five.
> I got a warning that the project would be converted to a new
> format not usable by older versions; and a promise the old
> version would be zipped somewhere (yet to check that, but I
> have the source on my DPS disk beyond any alien access anyway).
> The the project got open, but the Abel source was gone; the
> top source now was its translation to vhdl.
 Fair enough, I thought,
> I was warned for that sort of thing.

Err No. I'd say NOT fair-enough.
WHY should they need to replace YOUR source code ?

If they have Abel-to-VHDL working, then simply run that in the
background.

I was told by a friend a couple of years back, that was how Xilinx
handled his abel - it did VHDL spins, but they were 'hidden', and it
took Xilinx a few months to knock the edges off that change, but it
DID sound like it all worked.

> What I was not warned of
> was the fact that it would no longer work... It just won't
> compile, I think it does not preserve the pin numbers I
> have assigned in the Abel file.
> I suppose it can be tweaked to eventually work, if there
> were any sane reason why someone would want to do that.
> I don't, that's sure :-).
> But I was reminded once more why it is so important
> to have all design tools under control, the coolrunner
> series is the finest programmable silicon I have seen and
> I clearly will have to adapt my lc to the 3 and perhaps
> 2 series, hopefully they will live for another while.

 Have you looked at the Atmel ATF1508RE ?
I use the CUPL tool flows on their ATF15xx family.
 It compiles in a fraction of a second, has a stable, flash-Drivable
image and it can create test vector files.
 Hooked to a button in my favourite text editor.
Simple.Stable.Bulletproof (well, almost: Zero Angst)

-jg

On Nov 11, 11:13=A0am, -jg <jim.granvi...@gmail.com> wrote:
> ....
> I've sent Dimiter a disk image of an .ABL project compiled into a
> XCR3128, so he can check what has changed....

While having my morning coffee at 11 PM (still half full) I tried
the newest version I have here (ISE11) on my test project, the one
with the one toggling bit shifting through another five.
I got a warning that the project would be converted to a new
format not usable by older versions; and a promise the old
version would be zipped somewhere (yet to check that, but I
have the source on my DPS disk beyond any alien access anyway).
The the project got open, but the Abel source was gone; the
top source now was its translation to vhdl. Fair enough, I thought,
I was warned for that sort of thing. What I was not warned of
was the fact that it would no longer work... It just won't
compile, I think it does not preserve the pin numbers I
have assigned in the Abel file.
I suppose it can be tweaked to eventually work, if there
were any sane reason why someone would want to do that.
I don't, that's sure :-).
But I was reminded once more why it is so important
to have all design tools under control, the coolrunner
series is the finest programmable silicon I have seen and
I clearly will have to adapt my lc to the 3 and perhaps
2 series, hopefully they will live for another while.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/

On Nov 11, 11:13=A0am, -jg <jim.granvi...@gmail.com> wrote:
> On Nov 11, 9:09=A0pm, Antti <antti.luk...@googlemail.com> wrote:
>
> > > This is a legacy tool chain, but Xilinx can't have broken any of this=
,
> > > on newer versions can they ?! ;)
>
> > > -jg
>
> > sure they can
> > break any legacy with any minor update of the tools
> > they can
>
> Antti - Did you miss the winky =A0?? =A0;)
>
> I've sent Dimiter a disk image of an .ABL project compiled into a
> XCR3128, so he can check what has changed....
>
> Who knows, the gods might even smile, and given him the same
> answer...?!
>
> -jg

Thanks Jim, I'll hopefully know more after some sleep (dead tired
now). Why am I getting to sleep at 12 AM is another story, I get
out of sync sometimes and the I get back an hour per day (yesterday
it was 10 AM but today I pushed it some more).

Dimiter

On Nov 11, 9:09=A0pm, Antti <antti.luk...@googlemail.com> wrote:
> > This is a legacy tool chain, but Xilinx can't have broken any of this,
> > on newer versions can they ?! ;)
>
> > -jg
>
> sure they can
> break any legacy with any minor update of the tools
> they can

Antti - Did you miss the winky  ??  ;)

I've sent Dimiter a disk image of an .ABL project compiled into a
XCR3128, so he can check what has changed....

Who knows, the gods might even smile, and given him the same
answer...?!

-jg

On Nov 11, 9:46=A0am, -jg <jim.granvi...@gmail.com> wrote:
> On Nov 11, 7:24=A0pm, -jg <jim.granvi...@gmail.com> wrote:
>
> > On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote:
>
> > > I will of course still welcome all help, I am still far from
> > > done with this.
>
> > > Dimiter
>
> > I have a handful of ABL files on a Xilinx stub here, I can compile
> > those and zip the results if you give an email ?
>
> > -jg
>
> I've blown the dust off the directory(s), and it barfed on converting
> the old projects - but it happily made new ones.
> * new Project =A0(name becomes subdir)
> * right click add source [select .ABL file]
> * double click on device, select XCR3128XL
> * click on source
> =A0 * Double click on Fitter report in process list
> =A0 * Double click on =A0generate Jtag file in process list
>
> and voila, truckloads of files, but the ones that matter are .rpt,
> and
> .jed
>
> If I right-click on [fit].properties, I can select HDL equation style,
> where you can choose Source/ABEL/Verilog/VHDL, and that's what it uses
> in the fitter report files. - select the most readable
>
> This is a legacy tool chain, but Xilinx can't have broken any of this,
> on newer versions can they ?! ;)
>
> -jg

sure they can
break any legacy with any minor update of the tools
they can

Antti

On Nov 11, 7:24=A0pm, -jg <jim.granvi...@gmail.com> wrote:
> On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote:
>
> > I will of course still welcome all help, I am still far from
> > done with this.
>
> > Dimiter
>
> I have a handful of ABL files on a Xilinx stub here, I can compile
> those and zip the results if you give an email ?
>
> -jg

I've blown the dust off the directory(s), and it barfed on converting
the old projects - but it happily made new ones.
* new Project  (name becomes subdir)
* right click add source [select .ABL file]
* double click on device, select XCR3128XL
* click on source
  * Double click on Fitter report in process list
  * Double click on  generate Jtag file in process list

and voila, truckloads of files, but the ones that matter are .rpt,
and
.jed

If I right-click on [fit].properties, I can select HDL equation style,
where you can choose Source/ABEL/Verilog/VHDL, and that's what it uses
in the fitter report files. - select the most readable

This is a legacy tool chain, but Xilinx can't have broken any of this,
on newer versions can they ?! ;)

-jg