>One of the simplest and most consistent multiplexers I've used is with
>arrays of registers or wires.
>
>wire [p:0] my_sel;
>wire [n:0] my_array [m:0];  // assign m+1 my_array values to the
>desired inputs
>reg [n:0] my_output;
>//
>always @(posedge clk)  my_output <=3D my_array[my_sel];
>
Thanks John that works great.

Jon	   
					
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On Jan 1, 4:51=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> I would like to create a generic multiplexer in Verilog were I can set th=
e
> number of inputs and data bits. I can create something using 2 input
> multiplexers cascaded but this produces a priority structure which uses
> more logic resources. If anyone can give me a clue as to if it is possibl=
e
> that would be great.
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com

One of the simplest and most consistent multiplexers I've used is with
arrays of registers or wires.

wire [p:0] my_sel;
wire [n:0] my_array [m:0];  // assign m+1 my_array values to the
desired inputs
reg [n:0] my_output;
//
always @(posedge clk)  my_output <=3D my_array[my_sel];

On Fri, 2010-01-01 at 06:16 -0600, maxascent wrote:=20
> I did a quick experiment using Synplify were I created 2 multiplexers of =
4
> inputs with 64-bit data, one using my cascaded 2 input mux and another
> using a case statement. The one with the case statement used less resorce=
s.
> So either I have coded the first incorrectly or Synplify is interpreting
> the code differently.

I did the experience that is depends on the FPGA type (Lut type, ...)
and vendor (maybe tools). So, I think it is a good practice to test
it for the different factors.

cheers
ben

I did a quick experiment using Synplify were I created 2 multiplexers of 4
inputs with 64-bit data, one using my cascaded 2 input mux and another
using a case statement. The one with the case statement used less resorces.
So either I have coded the first incorrectly or Synplify is interpreting
the code differently.

Jon	   
					
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This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

maxascent <maxascent@yahoo.co.uk> wrote:

> I would like to create a generic multiplexer in Verilog were I can set the
> number of inputs and data bits. I can create something using 2 input
> multiplexers cascaded but this produces a priority structure which uses
> more logic resources. If anyone can give me a clue as to if it is possible
> that would be great.

The synthesis tools that I know of will easily optimize out any
difference that you might be thinging about, at least for FPGA
targets.  (You did post to comp.arch.fpga.)

That is especially true for LUT4 architecture FPGAs.  I believe
the usual generated form is more like an N to 2**N decoder,
followed by AND/OR logic.  That is especially true if it is
more than one bit wide, which requires only one decoder.

-- glen

I would like to create a generic multiplexer in Verilog were I can set the
number of inputs and data bits. I can create something using 2 input
multiplexers cascaded but this produces a priority structure which uses
more logic resources. If anyone can give me a clue as to if it is possible
that would be great.

Jon	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com