On Jan 20, 7:46=A0am, "jjlind...@hotmail.com" <jjlind...@hotmail.com>
wrote:
> On Jan 18, 2:50=A0am, Charles Gardiner <inva...@invalid.invalid> wrote:
>
> > > Thanks everyone for your input. My question is relating to the cost o=
f
> > > a simulator that supports SystemVerilog Verfication, just how much
> > > should I expect to spend for one license? If its too expensive I'll
> > > have to stick with sytem testbenches.
>
> > > joe
>
> > To put a ball park on it, about the price of a relatively well-equiped
> > medium range car ;). If you get a great deal from Aldec / Cadence /
> > Mentor / Synopsys, maybe the price of a well equiped small car.
>
> Why is it so expensive?
Not sure! But I was completely blown away at how much discounts are
offered if you just ask for them... the car analogy really applies
here. Even better would be a "used car"... i.e. you bargain as if you
are out to buy a used car. Nevertheless, if you want a cheap tool to
learn Aldec Riviera Pro may be a good deal as well... ofcourse, here
you pay to debug Riviera for Aldec.
Reply by jjli...@hotmail.com●January 20, 20102010-01-20
On Jan 18, 2:50=A0am, Charles Gardiner <inva...@invalid.invalid> wrote:
> > Thanks everyone for your input. My question is relating to the cost of
> > a simulator that supports SystemVerilog Verfication, just how much
> > should I expect to spend for one license? If its too expensive I'll
> > have to stick with sytem testbenches.
>
> > joe
>
> To put a ball park on it, about the price of a relatively well-equiped
> medium range car ;). If you get a great deal from Aldec / Cadence /
> Mentor / Synopsys, maybe the price of a well equiped small car.
Why is it so expensive?
Reply by Charles Gardiner●January 18, 20102010-01-18
> Thanks everyone for your input. My question is relating to the cost of
> a simulator that supports SystemVerilog Verfication, just how much
> should I expect to spend for one license? If its too expensive I'll
> have to stick with sytem testbenches.
>
> joe
To put a ball park on it, about the price of a relatively well-equiped
medium range car ;). If you get a great deal from Aldec / Cadence /
Mentor / Synopsys, maybe the price of a well equiped small car.
> Thanks everyone for your input. My question is relating to the cost of
> a simulator that supports SystemVerilog Verfication, just how much
> should I expect to spend for one license? If its too expensive I'll
> have to stick with sytem testbenches.
If you have to ask you can't afford it...
Anyway you should check with Mentor, maybe they can give you a deal.
I've never used Questa myself, only Synopsys VCS.
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Reply by jjli...@hotmail.com●January 15, 20102010-01-15
On Jan 15, 2:40=A0pm, Anssi Saari <a...@sci.fi> wrote:
> Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> writes:
> > You will probably find that quite a few of the SV design features
> > are fully supported in that version - interfaces, always_comb,
> > structs, .* port connection, that sort of thing - but I would
> > be astonished if you had access to any of the big-ticket
> > verification stuff such as classes and randomization. =A0To
> > find out, try these little examples. =A0Be sure to give the
> > files ".sv" extension, or alternatively use the -sv compile
> > option to the vlog command.
>
> Well, since all I have at home is the Altera free edition and in fact
> it seems it's the only free Modelsim out for Linux right now (well,
> Actel has a 45 day trial), I tried these out. Only example complains
> about missing support:
>
> Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct =A01 2009
> -- Compiling module random_test
> ** Warning: ex2.sv(5): (vlog-2186) SystemVerilog testbench feature
> (randomization, coverage or assertion) detected in the design.
> These features are only supported in Questasim.
>
> And trying to run it gives:
>
> # vsim random_test =A0 =A0 =A0
> # Loading sv_std.std
> # Loading work.random_test
> VSIM 3> run -all
> # ** Fatal: ex2.sv(5): Unable to check out verification license for rando=
> # Fatal error in Module random_test at ex2.sv line 5
> #
> # HDL call sequence:
> # Stopped at ex2.sv 5 Module random_test
>
> But all the others work. Not bad for a freebie...
Thanks everyone for your input. My question is relating to the cost of
a simulator that supports SystemVerilog Verfication, just how much
should I expect to spend for one license? If its too expensive I'll
have to stick with sytem testbenches.
joe
Reply by Anssi Saari●January 15, 20102010-01-15
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes:
> You will probably find that quite a few of the SV design features
> are fully supported in that version - interfaces, always_comb,
> structs, .* port connection, that sort of thing - but I would
> be astonished if you had access to any of the big-ticket
> verification stuff such as classes and randomization. To
> find out, try these little examples. Be sure to give the
> files ".sv" extension, or alternatively use the -sv compile
> option to the vlog command.
Well, since all I have at home is the Altera free edition and in fact
it seems it's the only free Modelsim out for Linux right now (well,
Actel has a 45 day trial), I tried these out. Only example complains
about missing support:
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module random_test
** Warning: ex2.sv(5): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
And trying to run it gives:
# vsim random_test
# Loading sv_std.std
# Loading work.random_test
VSIM 3> run -all
# ** Fatal: ex2.sv(5): Unable to check out verification license for randomize() feature.
# Time: 0 ps Iteration: 0 Process: /random_test/#INITIAL#3 File: ex2.sv
# Fatal error in Module random_test at ex2.sv line 5
#
# HDL call sequence:
# Stopped at ex2.sv 5 Module random_test
But all the others work. Not bad for a freebie...
Reply by HT-Lab●January 15, 20102010-01-15
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in
message news:7rbm1tFrl4U1@mid.individual.net...
>> Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>> that be okay?
>
> As the others have said probably not.
>
> The OEM /Starter Editions are all knobbled a bit, they run at reduced
> speed or functionality.
>
> The base 'normal' spec of Modelsim is PE (Properly Expensive), this is
> superceded by SE (Specially Expensive).
:-)
>
>
> [Particularly here in the UK where tools prices seem to be the same in �
> as the guys from the States get them in $ (�1 ~ $1.6)]
"Mark Curry" <gtwrek@sonic.net> wrote in message
news:4b509c09$0$1597$742ec2ed@news.sonic.net...
> In article <oi51l5dco9u5ncgo207pg8s8s4g6b0mb83@4ax.com>,
> Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:
>>On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote:
>>
>>[me]
>>>> using SystemVerilog's object-oriented programming features,
>>>> and those definitely require top-end features of the simulator
>>>> that you simply won't get in the cheaper or "student" editions.
>>
>>[you]
>>>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>>>that be okay?
>>
>>I'm afraid not.
>>
>>You will probably find that quite a few of the SV design features
>>are fully supported in that version - interfaces, always_comb,
>>structs, .* port connection, that sort of thing - but I would
>>be astonished if you had access to any of the big-ticket
>>verification stuff such as classes and randomization. To
>>find out, try these little examples. Be sure to give the
>>files ".sv" extension, or alternatively use the -sv compile
>>option to the vlog command.
>>
> <snipped (good!) examples>
>
> Actually, modelsim SE supports a large set of SystemVerilog.
> All the examples work except for example 2 with
> Modelsim SE. SE supports all of the "design" features
> of SystemVerilog as well as SystemVerilog classes.
> You need Questa for the constraint solver and SystemVerilog
> Assertions.
SVA (and PSL) are supported in Modelsim DE (much cheaper than SE/Questa and it
runs under Linux :-), but you are correct regarding the rest.
Hans
www.ht-lab.com
> Which makes sense as that's the harder
> problem to solve for tool vendors.
>
> Now, I'm using SE - which is NOT a "Starter Edition" as the OP indicated.
> I thought the starter product was "DE" or something like that.
>
> Your mileage may vary - Mentor likes to slice and dice their
> product definition / licensing to (confusing) extremes...
>
> --Mark
>
Reply by Nial Stewart●January 15, 20102010-01-15
> Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
> that be okay?
As the others have said probably not.
The OEM /Starter Editions are all knobbled a bit, they run at reduced
speed or functionality.
The base 'normal' spec of Modelsim is PE (Properly Expensive), this is
superceded by SE (Specially Expensive).
[Particularly here in the UK where tools prices seem to be the same in �
as the guys from the States get them in $ (�1 ~ $1.6)]
Nial.
Reply by Mark Curry●January 15, 20102010-01-15
In article <oi51l5dco9u5ncgo207pg8s8s4g6b0mb83@4ax.com>,
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:
>On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote:
>
>[me]
>>> using SystemVerilog's object-oriented programming features,
>>> and those definitely require top-end features of the simulator
>>> that you simply won't get in the cheaper or "student" editions.
>
>[you]
>>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>>that be okay?
>
>I'm afraid not.
>
>You will probably find that quite a few of the SV design features
>are fully supported in that version - interfaces, always_comb,
>structs, .* port connection, that sort of thing - but I would
>be astonished if you had access to any of the big-ticket
>verification stuff such as classes and randomization. To
>find out, try these little examples. Be sure to give the
>files ".sv" extension, or alternatively use the -sv compile
>option to the vlog command.
>
<snipped (good!) examples>
Actually, modelsim SE supports a large set of SystemVerilog.
All the examples work except for example 2 with
Modelsim SE. SE supports all of the "design" features
of SystemVerilog as well as SystemVerilog classes.
You need Questa for the constraint solver and SystemVerilog
Assertions. Which makes sense as that's the harder
problem to solve for tool vendors.
Now, I'm using SE - which is NOT a "Starter Edition" as the OP indicated.
I thought the starter product was "DE" or something like that.
Your mileage may vary - Mentor likes to slice and dice their
product definition / licensing to (confusing) extremes...
--Mark