>
>
> "Jim Wu" <NOSPAM@NOSPAM.com> schrieb im Newsbeitrag
> news:R8Umc.29892$wY.21792@nwrdny03.gnilink.net...
> > > in order to verify the functionality of XILINX DCM, I have
generated a
> > > dcm.vhd file with the ISE 6.2 architecture wizard. The dcm
module is
> > > embedded into a simple top-level file that only connects the
testbench
> > > signals (in-clock and reset (=0) to the DCM-module. The DCM
reset
> > > signal is always set to '0'.
> > >
> >
> > It would help if you can post the testbench code as well.
Sometimes the
> > generation of the inputs to the DCM may affect the behavior
simulation
> > model. I've seen that DCM model does not work if the input clock
starts at
> 1
> > at time 0. e.g
> >
> > process
> > clock_in <= '1';
> > wait for 10ns;
> > clock_in <= '0';
> > wait for 10ns;
> > end process;
> >

Also check time resolution of the simulation is set to picoseconds -
it
should be if you launch the simulation from ISE, but if you are
running
Modelsim "manually" you need to do vsim -t ps, r

regards

Alan

-- 
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Consultant

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views of Doulos Ltd., unless specifically stated.

hi!

try to reset the dcm after 3 or more clk cycles of clkin. hold the reset for
about 3 or more clk cycles

best regards

wolfgang


"Jim Wu" <NOSPAM@NOSPAM.com> schrieb im Newsbeitrag
news:R8Umc.29892$wY.21792@nwrdny03.gnilink.net...
> > in order to verify the functionality of XILINX DCM, I have generated a
> > dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is
> > embedded into a simple top-level file that only connects the testbench
> > signals (in-clock and reset (=0) to the DCM-module. The DCM reset
> > signal is always set to '0'.
> >
>
> It would help if you can post the testbench code as well. Sometimes the
> generation of the inputs to the DCM may affect the behavior simulation
> model. I've seen that DCM model does not work if the input clock starts at
1
> at time 0. e.g
>
> process
> clock_in <= '1';
> wait for 10ns;
> clock_in <= '0';
> wait for 10ns;
> end process;
>
> HTH,
> Jim
> jimwu88NOOOSPAM@yahoo.com
> http://www.geocities.com/jimwu88/chips
>
>
>

I have modified the testbench, but nothing happens at the DCM output. 

from my testbench file:
------------------------
signal lclk : std_logic := '0';

  process (lclk)    -- Generate 100 Mhz clock (Periodendauer 10 ns)
  begin
    if lclk='0' then
      lclk <= '1' after 15 ns, '0' after 30 ns;
    end if;
  end process;
------------------------

Any ideas
J&#4294967295;rgen

"Jim Wu" <NOSPAM@NOSPAM.com> wrote in message news:<R8Umc.29892$wY.21792@nwrdny03.gnilink.net>...
> > in order to verify the functionality of XILINX DCM, I have generated a
> > dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is
> > embedded into a simple top-level file that only connects the testbench
> > signals (in-clock and reset (=0) to the DCM-module. The DCM reset
> > signal is always set to '0'.
> >
> 
> It would help if you can post the testbench code as well. Sometimes the
> generation of the inputs to the DCM may affect the behavior simulation
> model. I've seen that DCM model does not work if the input clock starts at 1
> at time 0. e.g
> 
> process
> clock_in <= '1';
> wait for 10ns;
> clock_in <= '0';
> wait for 10ns;
> end process;
> 
> HTH,
> Jim
> jimwu88NOOOSPAM@yahoo.com
> http://www.geocities.com/jimwu88/chips

Hi Jim,

the testbench part is here:


signal lclk : std_logic := '0';

  process (lclk)    -- Generate 100 Mhz clock (Periodendauer 10 ns)
  begin
    if lclk='0' then
      lclk <= '1' after 15 ns, '0' after 30 ns;
    end if;
  end process;

The clock works fine. But both outputs of the DCM are always '0'.

Any ideas
Juergen


"Jim Wu" <NOSPAM@NOSPAM.com> wrote in message news:<R8Umc.29892$wY.21792@nwrdny03.gnilink.net>...
> > in order to verify the functionality of XILINX DCM, I have generated a
> > dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is
> > embedded into a simple top-level file that only connects the testbench
> > signals (in-clock and reset (=0) to the DCM-module. The DCM reset
> > signal is always set to '0'.
> >
> 
> It would help if you can post the testbench code as well. Sometimes the
> generation of the inputs to the DCM may affect the behavior simulation
> model. I've seen that DCM model does not work if the input clock starts at 1
> at time 0. e.g
> 
> process
> clock_in <= '1';
> wait for 10ns;
> clock_in <= '0';
> wait for 10ns;
> end process;
> 
> HTH,
> Jim
> jimwu88NOOOSPAM@yahoo.com
> http://www.geocities.com/jimwu88/chips

> in order to verify the functionality of XILINX DCM, I have generated a
> dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is
> embedded into a simple top-level file that only connects the testbench
> signals (in-clock and reset (=0) to the DCM-module. The DCM reset
> signal is always set to '0'.
>

It would help if you can post the testbench code as well. Sometimes the
generation of the inputs to the DCM may affect the behavior simulation
model. I've seen that DCM model does not work if the input clock starts at 1
at time 0. e.g

process
clock_in <= '1';
wait for 10ns;
clock_in <= '0';
wait for 10ns;
end process;

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com
http://www.geocities.com/jimwu88/chips

Hi,
in order to verify the functionality of XILINX DCM, I have generated a
dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is
embedded into a simple top-level file that only connects the testbench
signals (in-clock and reset (=0) to the DCM-module. The DCM reset
signal is always set to '0'.

Unfortunately, during the simulation with Modelsim, I do not obtain
the 4x clock signal of the input clock at the output (CLKFX_OUT) but
always '0'. CLK0_OUT is always '0', but CLKIN_IBUFG_OUT follows the
input clock signal.

What can be the reason for this behavior ?

Regards
Juergen

------------------------------------------------------------------------------
Below: the dcm file generated by architecture wizard

-- Module dyna_dcm
-- Generated by Xilinx Architecture Wizard
-- VHDL
-- Written for synthesis tool: XST

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- synopsys translate_off
Library UNISIM;
use UNISIM.Vcomponents.all;
-- synopsys translate_on

entity dyna_dcm is
    port (
        RST_IN : in std_logic;
        CLKIN_IN : in std_logic;
        LOCKED_OUT : out std_logic;
        CLKFX_OUT : out std_logic;
        CLKIN_IBUFG_OUT : out std_logic;
        CLK0_OUT : out std_logic);
end dyna_dcm;

architecture STRUCT of dyna_dcm is
   signal CLKIN_IBUFG : std_logic;
   signal CLKFB_IN : std_logic;
   signal CLK0_BUF : std_logic;
   signal CLKFX_BUF : std_logic;
   signal GND : std_logic;

-- Period Jitter (unit interval) = 0.17 UI
-- Period Jitter (Peak-to-Peak) = 0.63 ns

   component DCM
    generic( 
       CLKDV_DIVIDE : real := 2.0;
       CLKFX_DIVIDE : integer := 1;
       CLKFX_MULTIPLY : integer := 4;
       CLKIN_DIVIDE_BY_2 : boolean := false;
       CLKIN_PERIOD : real := 0.0;                         
       CLKOUT_PHASE_SHIFT : string := "NONE";
       CLK_FEEDBACK : string := "1X";
       DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";     
       DFS_FREQUENCY_MODE : string := "LOW";
       DLL_FREQUENCY_MODE : string := "LOW";
       DSS_MODE : string := "NONE";                        
       DUTY_CYCLE_CORRECTION : boolean := true;
       FACTORY_JF : bit_vector := X"C080";                 
       MAXPERCLKIN : time := 1000000 ps;                   
       MAXPERPSCLK : time := 100000000 ps;                 
       PHASE_SHIFT : integer := 0;
       SIM_CLKIN_CYCLE_JITTER : time := 300 ps;            
       SIM_CLKIN_PERIOD_JITTER : time := 1000 ps;          
       STARTUP_WAIT : boolean := false                     
     );
     port (
       CLKIN : in std_logic;
       CLKFB : in std_logic;
       RST : in std_logic;
       PSEN : in std_logic;
       PSINCDEC : in std_logic;
       PSCLK : in std_logic;
       DSSEN : in std_logic;
       CLK0 : out std_logic;
       CLK90 : out std_logic;
       CLK180 : out std_logic;
       CLK270 : out std_logic;
       CLKDV : out std_logic;
       CLK2X : out std_logic;
       CLK2X180 : out std_logic;
       CLKFX : out std_logic;
       CLKFX180 : out std_logic;
       STATUS : out std_logic_vector (7 downto 0);
       LOCKED : out std_logic;
       PSDONE : out std_logic
       );
   end component;
   component IBUFG
     port (
       I : in std_logic;
       O : out std_logic
       );
   end component;
   component BUFG
     port (
       I : in std_logic;
       O : out std_logic
       );
   end component;

begin
   DCM_INST : DCM
    Generic map (
      CLK_FEEDBACK => "1X",
      CLKDV_DIVIDE => 2.0,
      CLKFX_DIVIDE => 1,
      CLKFX_MULTIPLY => 4,
      CLKIN_DIVIDE_BY_2 => FALSE,
      CLKIN_PERIOD => 15.1515,
      CLKOUT_PHASE_SHIFT => "NONE",
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
      DFS_FREQUENCY_MODE => "HIGH",
      DLL_FREQUENCY_MODE => "LOW",
      DUTY_CYCLE_CORRECTION => TRUE,
      PHASE_SHIFT => 0,
      STARTUP_WAIT => FALSE)
     port map (
      CLKIN => CLKIN_IBUFG,
      CLKFB => CLKFB_IN,
      RST => RST_IN,
      PSEN => GND,
      PSINCDEC => GND,
      PSCLK => GND,
      DSSEN => GND,
      CLK0 => CLK0_BUF,
      CLKFX => CLKFX_BUF,
      LOCKED => LOCKED_OUT);

   CLKIN_IBUFG_INST : IBUFG
     port map (
      I => CLKIN_IN,
      O => CLKIN_IBUFG);

   CLK0_BUFG_INST : BUFG
     port map (
      I => CLK0_BUF,
      O => CLKFB_IN);

   CLKFX_BUFG_INST : BUFG
     port map (
      I => CLKFX_BUF,
      O => CLKFX_OUT);

   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
   CLK0_OUT <= CLKFB_IN;
   GND <= '0';
end STRUCT;