Reply by Gabor August 26, 20102010-08-26
On Aug 26, 6:53=A0am, Bert_Paris <do_not_s...@me.com> wrote:
> Dans son message pr=E9c=E9dent, Bert_Paris a =E9crit :> for Altera FPGAs. > > I don't assume it's going to be useful for Xilinx (or Actel or Lattice) > users, since most of the work is about undesrtanding how to use the > *Altera* Megafunction named "altremote_update"... > Bert
Oh, I assumed that Startan III was an Alterinx product like Stratex 7 :)
Reply by Bert_Paris August 26, 20102010-08-26
Dans son message pr&#4294967295;c&#4294967295;dent, Bert_Paris a &#4294967295;crit :
> for Altera FPGAs.
I don't assume it's going to be useful for Xilinx (or Actel or Lattice) users, since most of the work is about undesrtanding how to use the *Altera* Megafunction named "altremote_update"... Bert
Reply by Nial Stewart August 26, 20102010-08-26
> Bert, there's only one page in the PDF (numbering shows 1 of 9) !
...and as he's just pointed out by email there's a link to the whole thing at the bottom. Nial.
Reply by Nial Stewart August 26, 20102010-08-26
> Anyone spotting a discrepancy, please let me know.
Bert, there's only one page in the PDF (numbering shows 1 of 9) ! Nial.
Reply by Nial Stewart August 26, 20102010-08-26
> After seeing a number of customers struggling with this issue, I have written a detailed ApNote > showing how to implement a multiple configuration system for Altera FPGAs.
Thanks for this Bert, I have to get remote-update / multiple configuration operating on a Startan III board immenently so this is very useful. One thing, when I skimmed your post I presumed you were talking about configuring multiple devices from one flash chip, not multiple images for one device. Nial.
Reply by Bert_Paris August 25, 20102010-08-25
Hi,

After seeing a number of customers struggling with this issue, I have 
written a detailed ApNote showing how to implement a multiple 
configuration system for Altera FPGAs. The example is a Cyclone III 
using Active Serial mode / EPCS (on a DE0 board), but it is easily 
translatable to any other Altera FPGA/board.
It is not complex, but getting everything right from the documentation 
is not absolutely obvious.
The ApNote and the design files are available at the top of the list 
at:
http://www.alse-fr.com/apnotes.php
Anyone spotting a discrepancy, please let me know.

Hope this helps,
Bert.