If you place output FFs into IOBs you should have no problem meeting DAC's 
setup/hold requirements. If you still do, consider making the clock trace 
longer on PCB or using a clock distribution chip with a programmable delay 
such as e.g. AD9510. Finally, some of the modern high-speed DACs can 
automatically adjust their sampling time of the input data internally.

/Mikhail

On Sun, 29 Aug 2010 14:14:21 -0700 (PDT), Sharath Raju <brsharath@gmail.com>
wrote:

>Hello everyone,
>
>We are building a board in which we propose to design the FPGA
>interface to a DAC in the following manner. Please give feedback
>whether such an approach is feasible.

>The question is this:
>Assuming the clock is routed on the PCB such that there is no phase
>delay between the ADC, DAC and the FPGA, can the data output by the
>FPGA be delayed by say half a clock cycle 
...
>Instead, can we use timing contraints to achieve the phase delay ?

Probably not, but you can certainly clock the output data from the opposite
clock edge.

Alternatively, set the internal clock phase using the DCM to give the outputs
the best timing window, and look at IOB delays (IOBDELAY constraint, or IDELAY
blocks, depending on device family - I can't remember what the S3ADSP gives you)
to control the input timing.

- Brian

On Aug 29, 5:14=A0pm, Sharath Raju <brshar...@gmail.com> wrote:
> Hello everyone,
>
> We are building a board in which we propose to design the FPGA
> interface to a DAC in the following manner. Please give feedback
> whether such an approach is feasible.
>
> Functionality:
> Among other things, the board contains three components: ADC, DAC and
> FPGA (XC3SD1800A, Spartan 3ADSP 1.8 million gates). The ADC & DAC are
> connected to the FPGA. The ADC, DAC and FPGA are all clocked at 250
> MHz from an external clock source. To test whether ADC, DAC & FPGA are
> working fine, we propose to use the FPGA as a pipe from the ADC to the
> DAC. In this way, the output of the DAC should resemble the analog
> input.
>
> The question is this:
> Assuming the clock is routed on the PCB such that there is no phase
> delay between the ADC, DAC and the FPGA, can the data output by the
> FPGA be delayed by say half a clock cycle in order to satisfy the
> setup & hold consideration of the DAC. The trouble is we cannot use a
> DCM to phase-delay the clock inside the FPGA because the jitter-
> performance of the DCM is very poor compared to the input clock.
> Instead, can we use timing contraints to achieve the phase delay ?
>
> Thanks,
> Sharath

The IOBs tend to have delay elements built in.

But you may not be giving the DCM enough credit.  You want your clock
to be pure feeding both the DAC and ADC.  But a phase-shifted internal
clock can provide the needed setup and hold for the data from the ADC
and the appropriate clock-to-out valid window for the DAC.  Some high
speed ADCs are even designed to forward a regenerated (or
appropriately delayed) clock along with the data to the FPGA.

If you use a DCM in your clock path with timing constraints for OFFSET
IN and OFFSET OUT constraints, you should have less pushback from the
tools.  Without that help, the clock-to-out timing becomes a bit too
difficult to tie down to the proper window in a 4ns period in most
FPGA families.

Hello everyone,

We are building a board in which we propose to design the FPGA
interface to a DAC in the following manner. Please give feedback
whether such an approach is feasible.

Functionality:
Among other things, the board contains three components: ADC, DAC and
FPGA (XC3SD1800A, Spartan 3ADSP 1.8 million gates). The ADC & DAC are
connected to the FPGA. The ADC, DAC and FPGA are all clocked at 250
MHz from an external clock source. To test whether ADC, DAC & FPGA are
working fine, we propose to use the FPGA as a pipe from the ADC to the
DAC. In this way, the output of the DAC should resemble the analog
input.

The question is this:
Assuming the clock is routed on the PCB such that there is no phase
delay between the ADC, DAC and the FPGA, can the data output by the
FPGA be delayed by say half a clock cycle in order to satisfy the
setup & hold consideration of the DAC. The trouble is we cannot use a
DCM to phase-delay the clock inside the FPGA because the jitter-
performance of the DCM is very poor compared to the input clock.
Instead, can we use timing contraints to achieve the phase delay ?

Thanks,
Sharath