I have checked this before. A guy from edaboard gave me this advice but
they just got PLL with BGA package. About why i dont want to use BGA?
Becouse is much more expensive for assemble. Well i cant say about other
countries. But in Brazil it is.
But thank you for the advice. And just for information. This is not
intended for a comercial product in a low range time. Its for R&D
purposes.
Cya
---------------------------------------
Posted through http://www.FPGARelated.com
Reply by Frank Buss●October 18, 20102010-10-18
rickman wrote:
> BTW, even lower cost than the Lattice XP parts is the Silicon Blue
> iCE65 part line. The smallest parts are around $2-$3 and also come in
> 100 TQFP or even smaller chip scale packages.
Sounds interesting, but the shop at "buy online" shows only "call" for the
price for all parts, and "call" for "quantity avail." for most parts. Are
you sure you can really buy it in small quantities and less than some
months delivery time?
--
Frank Buss, http://www.frank-buss.de
piano and more: http://www.youtube.com/user/frankbuss
Reply by rickman●October 18, 20102010-10-18
On Oct 17, 6:07=A0pm, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
wrote:
> >In general, you don't need to worry about FPGA or CPLD parts being
> >discontinued for many years. =A0For example, if you really need them,
> >Xilinx still ships parts they originally built 15 years ago! =A0The
> >other companies are the same. =A0They just get more expensive after 8 or
> >10 years.
>
> >If price and size is important I would recommend that you look at the
> >XP Flash based FPGA family from Lattice. =A0Yes, Lattice is not Atmel,
> >but you said you wanted to optimize the design, not the development
> >process. =A0Pick one.
>
> >You can get 3 kLUTs in a 100 pin QFP for under $10 in quantity,
> >LFXP3C-3TN100C. =A0Mouser typically has stock of a couple hundred or
> >so. =A0Otherwise it is 8 week delivery.
>
> >Rick
>
> Yea. I will take a look on that! Thank you for your advice! That might he=
lp
> a lot. But just wondering, why you wrote that Lattice is not Atmel? Did n=
ot
> understand that.
>
> Any other sugestions are still apreciated. =A0 =A0 =A0 =A0
Opps, I meant Altera... you said you wanted to stick with Altera and
Lattice is not Altera.
BTW, even lower cost than the Lattice XP parts is the Silicon Blue
iCE65 part line. The smallest parts are around $2-$3 and also come in
100 TQFP or even smaller chip scale packages.
Rick
Reply by Sink0●October 17, 20102010-10-17
>
>In general, you don't need to worry about FPGA or CPLD parts being
>discontinued for many years. For example, if you really need them,
>Xilinx still ships parts they originally built 15 years ago! The
>other companies are the same. They just get more expensive after 8 or
>10 years.
>
>If price and size is important I would recommend that you look at the
>XP Flash based FPGA family from Lattice. Yes, Lattice is not Atmel,
>but you said you wanted to optimize the design, not the development
>process. Pick one.
>
>You can get 3 kLUTs in a 100 pin QFP for under $10 in quantity,
>LFXP3C-3TN100C. Mouser typically has stock of a couple hundred or
>so. Otherwise it is 8 week delivery.
>
>Rick
>
Yea. I will take a look on that! Thank you for your advice! That might help
a lot. But just wondering, why you wrote that Lattice is not Atmel? Did not
understand that.
Any other sugestions are still apreciated.
---------------------------------------
Posted through http://www.FPGARelated.com
Reply by rickman●October 17, 20102010-10-17
On Oct 17, 9:51 am, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
wrote:
> The idea of using the uC or DSP is considered at some cases but not always.
> The processin requiriments of every node of the network are completely
> different. Some nodes might just need a simple 16 bits uC or maybe a 300Mhz
> DSP. I cannot say that it would be a general solution.
>
> About the price. Yes i still have to evaluate the price of the Flash+FPGA
> compared to the FPGA with internal Flash. About using an external PLL, i
> really cant answer as i never used one for clock generation. I dont know if
> i can find an external PLL that can generate 2 outputs, and one shifted 90
> degrees from the other. How about the skew problem between both outputs.
> The clock lines would have to be very well designed no?
>
> Any comment about one Cyclone I is getting discontinued?
In general, you don't need to worry about FPGA or CPLD parts being
discontinued for many years. For example, if you really need them,
Xilinx still ships parts they originally built 15 years ago! The
other companies are the same. They just get more expensive after 8 or
10 years.
If price and size is important I would recommend that you look at the
XP Flash based FPGA family from Lattice. Yes, Lattice is not Atmel,
but you said you wanted to optimize the design, not the development
process. Pick one.
You can get 3 kLUTs in a 100 pin QFP for under $10 in quantity,
LFXP3C-3TN100C. Mouser typically has stock of a couple hundred or
so. Otherwise it is 8 week delivery.
Rick
Reply by Sink0●October 17, 20102010-10-17
The idea of using the uC or DSP is considered at some cases but not always.
The processin requiriments of every node of the network are completely
different. Some nodes might just need a simple 16 bits uC or maybe a 300Mhz
DSP. I cannot say that it would be a general solution.
About the price. Yes i still have to evaluate the price of the Flash+FPGA
compared to the FPGA with internal Flash. About using an external PLL, i
really cant answer as i never used one for clock generation. I dont know if
i can find an external PLL that can generate 2 outputs, and one shifted 90
degrees from the other. How about the skew problem between both outputs.
The clock lines would have to be very well designed no?
Any comment about one Cyclone I is getting discontinued?
Thank you!
---------------------------------------
Posted through http://www.FPGARelated.com
Reply by Michael S●October 16, 20102010-10-16
On Oct 15, 5:30=A0pm, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
wrote:
> Hi, i need to create a M-LVDS nwtwork running at 50-100Mbps. As i could n=
ot
> find any driver that could be placed to run that multdrop network (any
> protocol and datalink designed with small and size variable packet (Max 2=
56
> bytes) would be suitable) i designed one myself on a FPGA. On the on the
> uC/DSP side there is a 8/16 bits parallel interface and at the M-LVDS the
> clock is recovered with oversampling the data (using the rise and fall ed=
ge
> and a second clock with 90 degree phase as described in this paper:http:/=
> .
>
> The fisrt questions is: Is possible to implement such oversampling on a
> CPLD? Does CPLDs got any kind of PLL or something like that?
>
> Second: Do you think CPLDs are going to stay on the market for a long tim=
e?
> Or they are going to disapear and there will be just FPGAs?
>
> Third: This device must got a real small footprint. The best i found was =
a
> EP1C3 of Altera, but any one knows how long is going to take until this
> device is discontinued?
>
> Any sugestion of using a CPLD or FPGA for this design, or sugestions of a=
ny
> small fottprint (no BGA) FPGA of Altera or Xilinx (i got the download cab=
le
> of both and dont want to get a new one).
>
> Thank you! =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com
Did you consider completely dropping uC/DSP and building design in
System-On-Programmable-Chip style?
If the sw code and/or memory footprint is very small it's often no-
brainier.
If the sw code and/or memory footprint is too big to fit in on-chip
memory of uC/DSP it's also often no-brainier.
Only in the middle, where software fits in flash+SRAM of uC but
doesn't fit in internal memory of low-cost FPGA, the uC+FPGA ends up
more attractive.
Reply by Jaime Andres Aranguren C.●October 16, 20102010-10-16
"Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote in message
news:EI6dnTVfBZtCPiXRnZ2dnUVZ_v2dnZ2d@giganews.com...
>I dont really need LVDS as i am using an external tranceiver. Most of FPGAs
> LVDS ports cant drive a MLVDS bus. Not enough current. The MachXO is more
> expensive than a Cayclone and the smallest footprint is the same. But the
> best point is no need of external flash. I am not totally disconsidering
> other vendors, but i strongly prefer one that i got some experience and
> tools.
>
> Thank you!
>
> ---------------------------------------
> Posted through http://www.FPGARelated.com
>
Think in terms of system, not components only. What is more expensive in the
long run for your project: MachXO (or other flash based part) or FPGA +
Configuration memory? I am not saying the flash-based part will be the
winner here, only saying that it is worth comparing, and it all depends on
your project requirements.
Regards,
JaaC
Reply by Gabor●October 15, 20102010-10-15
On Oct 15, 2:56=A0pm, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
wrote:
> I dont really need LVDS as i am using an external tranceiver. Most of FPG=
As
> LVDS ports cant drive a MLVDS bus. Not enough current. The MachXO is more
> expensive than a Cayclone and the smallest footprint is the same. But the
> best point is no need of external flash. I am not totally disconsidering
> other vendors, but i strongly prefer one that i got some experience and
> tools.
>
> Thank you! =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com
I'm a long time Xilinx-user and found that the Lattice tools and
architecture are similar
enough that there was not a big learning curve. If you don't need
LVDS, then the only
other showstopper in a CPLD is how many flip-flops you have in the
design. FPGA's
are much richer in fabric flip-flops for a given size of part. Still
I don't remember seeing
PLL's in a real CPLD. Can you do it with a separate PLL part? You
can get some PLL's
intended for cleaning up clock jitter that have very good spec's in a
small TSSOP or
QFN package. Then if you don't need more flip-flops than are
reasonable in a CPLD
you can again find very small QFN parts. Any reason you don't want to
consider
BGA packages?
Regards,
Gabor
Reply by Sink0●October 15, 20102010-10-15
I dont really need LVDS as i am using an external tranceiver. Most of FPGAs
LVDS ports cant drive a MLVDS bus. Not enough current. The MachXO is more
expensive than a Cayclone and the smallest footprint is the same. But the
best point is no need of external flash. I am not totally disconsidering
other vendors, but i strongly prefer one that i got some experience and
tools.
Thank you!
---------------------------------------
Posted through http://www.FPGARelated.com