On Nov 24, 6:46=A0pm, John Smith <redditor...@gmail.com> wrote:
> Is it acceptable to have 2D input ports using System Verilog?

Sure. It allows just about anything: arrays, structures, interfaces
(obviously).  Now, whether your synthesis tool handles these
constructs is another question that needs to be asked of the vendor.

Is it acceptable to have 2D input ports using System Verilog?

I know it's not possible in Verilog. The only workaround I could think
of is to 'flatten' out the input port and use it; but that seems to be
messy inside loops. Is there any other workaround?