> I just have 1 fast LVDS data line. I need to have 10 bits of data
> in a register , every 5 clock cycles(DDR), coming from only 1
> differential data line.
>
> Dear Gurus,
>
> 1- Can I deserialize a 240 Mhz , LVDS, DDR input coming data using a
> 10:1 serdes ratio. (clk is also LVDS)
240 MHz shouldn't be a problem for the Spartan 6 pins.
> 2- I want to do it with data width = 1( D = 1), is it possible?
What's your question? Input or Output datawidth?
From my understanding you want a 1 bit input (240 MBit/s) deserialized
to 10 bit (@24 MBit/s) output, right?
Don't see any reason why this shouldn't work.
> 3- Do I have to put delay to clk inputs. If not why is there a delay
> element (IODELAY2) in xapp1064.pdf
What's the protocol you use for clock recovery/synchronization?
> 4- Do I have to use the pll concept. Is there any other solution?
> 5- In the documentation of spartan 6 deserialization 16:1 is shown
> but with a SDR rate. Can it be changed to DDR?
So again: what's the point here? I still don't get what you are trying
to do, but you might also be interested in XAPP460,
Lorenz
Reply by Serkan●December 10, 20102010-12-10
I just have 1 fast LVDS data line. I need to have 10 bits of data
in a register , every 5 clock cycles(DDR), coming from only 1
differential data line.
Dear Gurus,
1- Can I deserialize a 240 Mhz , LVDS, DDR input coming data using a
10:1 serdes ratio. (clk is also LVDS)
2- I want to do it with data width = 1( D = 1), is it possible?
3- Do I have to put delay to clk inputs. If not why is there a delay
element (IODELAY2) in xapp1064.pdf
4- Do I have to use the pll concept. Is there any other solution?
5- In the documentation of spartan 6 deserialization 16:1 is shown
but with a SDR rate. Can it be changed to DDR?
=================================================================
PS1: I am using Spartan 6, slx100, -3
PS2: I checked xapp1064.pdf, ug381.pdf, ds162.pdf. I need more info
on IODELAY2 and ISERDES2.
best regards
Serkan