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FPGARelated.com has been around since 2006 and has become over the years a very popular resource for Field-programmable gate array (FPGA) experts around the world.
The Designer's Guide to VHDL
Peter J. Ashenden
Memory Systems: Cache, DRAM, Disk
VHDL Starter's Guide
Designing with FPGAs and CPLDs
Advanced Digital Design with the Verilog HDL (2nd Edition)
Michael D. Ciletti
Circuit Design with VHDL
Volnei A. Pedroni
The Designer's Guide to VHDL, Volume 3, Third Edition
Peter J. Ashenden
Implementing multiple interrupts
by Aleksandar Kuktin sent on 2013-12-08 15:29:00
Hi all. Some time ago, I designed a small and simple CPU to go into a project I am sort-of work...
MachXO breakout board as a programmer
by Gergo sent on 2013-12-07 09:30:00
Hi! I'd like to use my MachXO Breakout Board as a programming device to program a custom MachXO c...
LCD test on Spartan 3E FPGA
by Tung Thanh Le sent on 2013-12-05 19:57:00
Hi, I got a problem that I cannot understand how to display on the LCD of Sp= artan 3E FPGA. Th...
by John Larkin sent on 2013-12-04 23:44:00
We're into this signal processing project, using a microZed/ZYNQ thing as the compute engine. ...
Use of hardware adders with long words to perform multiple additions in parallel
by Wojciech M. Zabolotny sent on 2013-12-01 07:00:00
I was solving a problem, when I needed to calculate every clock a sum of multiple values encoded on...
Verilog! How to work with modules?
by beginner sent on 2013-11-29 05:40:00
Hello! 1.sorry for my poor english 2.i have the following diagram to implement in verilog: http:/...
by youngejoe sent on 2013-11-29 04:41:00
Hello all Proposed idea from my research to date: Two FPGA encryption modules: Both will have an...
Free VHDL Testbench library for logging/reporting and checking. A good solution - simple and powerful
by Unknown sent on 2013-11-28 10:47:00
If you are making VHDL testbenches you should be writing proper log message= s. You should also mak...
Interface Xilinx KC705 to BeagleBone?
by pfraser sent on 2013-11-25 18:49:00
I'm playing with the idea of interfacing a BeagleBone (cheap dual ARM Cortex A8 board) to a Xilinx ...
Mill: FPGA version?
by Joseph H Allen sent on 2013-11-23 14:29:00
I've been wondering if there could be a successful (not too large, reasonable clock frequency) soft...