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Memory Systems: Cache, DRAM, Disk
VHDL Starter's Guide
VHDL Coding Styles and Methodologies
FPGAs: Instant Access
Circuit Design with VHDL
Volnei A. Pedroni
The Designer's Guide to VHDL
Peter J. Ashenden
XILINX Artix-7 DDR2-RAM-Controller
by Bodo sent on 2013-05-18 11:06:00
Hello, I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I have some "proble...
Linting tool setup
by RCIngham sent on 2013-05-16 10:40:00
Greetings all, Further to previous thread(s), has anyone here experience in setting up a linting ...
Any experience of Equivalence Checking tools?
by RCIngham sent on 2013-05-14 11:23:00
Greetings all, Has anyone hereabouts any experience with the use of Equivalence Checking tools in...
Modelsim ought to be cheaper
by Kevin Neilson sent on 2013-05-13 10:32:00
Why is Modelsim so expensive? It is a mature product and yet it segfaults = on me all the time. C...
Inferring Xilinx BlockRAM FIFO
by Kevin Neilson sent on 2013-05-13 09:42:00
The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any way t= o infer them? Probabl...
Catapult C floating point exp() function?
by Unknown sent on 2013-05-13 09:40:00
Hello all, I was wondering if catapult C HLS has a built in exp() for floating point numbers. If ...
Xilinx SDK 14.5 debug
by maxascent sent on 2013-05-11 15:59:00
I have a Microblaze design in SDK that I am trying to debug. I have an IP block with some registers ...
Low cost and/or small size CPU in an FPGA
by hamilton sent on 2013-05-01 12:54:00
What is the lowest cost and/or the smallest CPU in an FPGA. Can a CPU with reasonable code space ...
comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA (EP4CE22F17C6N) apples to apples.
by jleslie48 sent on 2013-04-29 14:54:00
the xilinx says it has 500,000 gates, the altera says it has 22,320 Logic elements (LEs) 594 Em...
FPGA Development Board with hard PowerPC
by studywireless sent on 2013-04-26 22:01:00
I am working on a channel emulator which is based on a FPGA development board and a custom based RF ...