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Welcome to FPGARelated.com !

FPGARelated.com has been around since 2006 and has become over the years a very popular resource for Field-programmable gate array (FPGA) experts around the world.

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Comp.Arch.FPGA

calculations of logic vectors and constant
by itay sent on 2014-08-21 21:44:00
what is the prefered option of arithmetic operations using logic vectors and constant? convert log... 

ZPU-based SoC for Numato Saturn board with DRAM
by mnentwig sent on 2014-08-18 11:11:00
Hi, this is a "public backup" of a holiday project maybe it's of use to someone: https://drive.... 

LVDS problem - Black magic anyone?
by Unknown sent on 2014-08-17 14:02:00
I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are conn... 

Has anyone forked any Xilinx IP?
by SP sent on 2014-08-14 12:58:00
What is the "recommended" way to do IP forking from Xilinx's repos? Not for public distribution but... 

Basic question: sequence of execution within FPGAs
by Unknown sent on 2014-08-13 10:51:00
Trying to get my head around FPGAs after 40 years of 2GLs. I can't seem to find a clear exposition ... 

Professional VHDL Examples?
by Unknown sent on 2014-08-13 08:50:00
Over the years I have taught myself Verilog and VHDL, and although I am qui= te comfortable with Ve... 

strange effect with tristate output
by Frank Buss sent on 2014-08-10 11:38:00
I'm using a XC95144XL, two pins are an input for a 5V signal, which have pullup resistors (3k3). Se... 

What is the content of "High-speed SERDES interfacing such as PCIe, SDI, SGMII, XAUI"
by fl sent on 2014-08-08 18:11:00
Hi, I read a job post which requires: High-speed SERDES interfacing such as PCIe, SDI, SGMII, XA... 

multicycle path - synplify pro
by alb sent on 2014-08-08 05:57:00
Hi everyone, I'm experiencing an issue with Synplify Pro E-2010.09A-1. I have to insert some mu... 

How can Spartan-6 interface with 10/100 Mb/s Ethernet?
by fl sent on 2014-08-05 09:46:00
Hi, I read LogiCORE IP AXI Ethernet Lite MAC (v1.01.b), which says that the Ethernet interface is... 

Latest Papers, Theses, Articles, etc

Free Range VHDL
by Bryan Mealy |
0

The no-frills guide to writing powerful code for you digital implementations.... Free Range VHDL
The Shock and Awe VHDL Tutorial
by Bryan Mealy |
0

The purpose of this tutorial is to provide students with a guide to help develop the skills necessar... The Shock and Awe VHDL Tutorial
VHDL Tutorial
by Peter J. Ashenden |
0

The purpose of this tutorial is to describe the modeling language VHDL. VHDL includes facilities for... VHDL Tutorial
VHDL handbook
by Hardi Electronics |
0

Introduction to Verilog
by Peter M. Nyasulu |
0

Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated ci... Introduction to Verilog
FPGA Implementation of Digital Filters
by Chi-Jui Chou |
0

Digital Filtering algorithms are most commonly implemented using general purpose digital signal proc... FPGA Implementation of Digital Filters
FPGAs!? Now What?
by Dave Vandenbout |
0

There are numerous requests in Internet forums that go something like this: "I am new to using FPGAs... FPGAs!? Now What?
Architecture of FPGAs and CPLDs: A Tutorial
by Stephen Brown |
0

This paper provides a tutorial survey of architectures of commercially available high-capacity fiel... Architecture of FPGAs and CPLDs: A Tutorial
Performance driven FPGA design with an ASIC perspective
by Andreas Ehliar |
0

FPGA devices are an important component in many modern devices. This means that it is important that... Performance driven FPGA design with an ASIC perspective
Architectures, Methods, and Tools for Distributed Run-time Reconfigurable FPGA-based Systems
by Dirk Koc |
-3

More than two decades in FPGA evolution have emerged in a multibillion US$ market and devices that a... Architectures, Methods, and Tools for Distributed Run-time Reconfigurable FPGA-based Systems