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VHDL Starter's Guide
Advanced Digital Design with the Verilog HDL (2nd Edition)
Michael D. Ciletti
FPGAs: Instant Access
Designing with FPGAs and CPLDs
VHDL Coding Styles and Methodologies
The Designer's Guide to VHDL
Peter J. Ashenden
ERROR:HDLCompilers:27 - "ipcore_dir/Cordic_atan_synth.v" line 61 Illegal redeclaration of 'Cordic_atan'
by Raviraj Makwana sent on 2014-04-18 10:06:00
unable to solve this error.I tried all the thing and check that there is no duplicate module..still ...
New Lattice FPGAs on 40nm ?
by Brane2 sent on 2014-04-18 06:50:00
I'm playing with Lattice's MachXO2 and ECP3 for a few months now and now that MachXO3 is about to co...
Spartan 3 JTAG problems
by Mike Perkins sent on 2014-04-17 08:37:00
Has anyone come across an issue where an XC3S200 is recognised in Impact; "Right Click to Add Devi...
Help: Altera megafunctions, Quartus II
by Bruce Varley sent on 2014-04-17 05:55:00
I'm an FPGA newbie, working with the freeware Altera Quartus II IDE. I used the megafunction build...
Nexys 4 FPGA Board
by marwen brikcha sent on 2014-04-16 21:54:00
Hi all I'm usinf Digilent Nexys 4 FPGA BOard and I won't to run LInux kernel on microblaze and I ...
more than 58'000 false paths...
by alb sent on 2014-04-15 20:46:00
Hi everyone, I started adding false paths to my design (see this thread for a context:
how to specify which feature for a license
by alb sent on 2014-04-15 09:32:00
Hi everyone, we have a license server that hosts both ACTEL_SUMMIT feature (1 seat) and ACTEL_V...
[cross-post] group on systemC language
by alb sent on 2014-04-15 06:59:00
Hi everyone, does anyone out there know a group specialized on systemc? I'm interested in tlm m...
Actel Designer on multiple cores
by alb sent on 2014-04-14 11:25:00
Hi everyone, I had my vbox running with one core only (out of 4 on the host) and Designer was r...
cloud design flow
by alb sent on 2014-04-14 10:19:00
Hi there, I was wondering if there's any one out there working with a cloud design flow which i...