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DSPEmbedded Systems

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Transfering image file to DDR RAM using EDK
by rashmic sent on 2015-01-30 10:31:00
Hi, I am working on Xilinx Spartan 3e Starter kit board which has DDR Ram. I have to transfer ima... 

Send a pulse across clocks
by Leo sent on 2015-01-30 03:27:00
Hello, I want to send a pulse from one clock domain to another, knowing tha= t from the time event ... 

Where in ISE/Vivado are the chip specific resources listed?
by Svenn sent on 2015-01-29 15:22:00
Hi, I am trying to create a comparison list between various FPGAs in the Xilinx universe. The uni... 

Vivado is intensely frustrating
by Rob Gaddi sent on 2015-01-28 14:45:00
So, the following ROM initialization code should be entirely synthesizable. Not so, according to t... 

Artix-7 tools, ISE vs Vivado
by Vladimir Ivanov sent on 2015-01-28 03:19:00
Hello, What are the practical pros and cons of using each of ISE or Vivado for the Artix-7 fa... 

Xilinx XST and initializing block RAMs
by Christopher Head sent on 2015-01-28 00:49:00
Hi all, I'm using XST 14.2 and trying to use block RAMs to store constant data (i.e. as ROMs) for ... 

Instantiating Components or Using Generate statements
by Abdulla873 sent on 2015-01-27 16:08:00
Hi Guys, Are there any differences between instantiating components and using generate statement ... 

Why two hold checks done byTimeQuest
by kaz sent on 2015-01-27 14:48:00
Hi, TimeQuest says it uses two hold checks per each setup check. The first hold check for previ... 

[RANT] XILINX, Are you freaking kidding me ?
by Simon sent on 2015-01-22 12:54:00
So I wanted to know if it was possible to update an old embedded-developmen= t kit license that's... 

Altera Cyclone II
by Michael sent on 2015-01-20 23:46:00
Hi, I have a Altera Cyclone II design where I am looking for a good way to make a complete rese... 

Latest Papers, Theses, Articles, etc

Introducing the Spartan 3E FPGA and VHDL
by Mike Field |

I want to help hackers take the plunge into the world of FPGAs-- Starting at purchasing an FPGA deve... Introducing the Spartan 3E FPGA and VHDL
FPGAs for Dummies - Altera Special Edition
by Andrew Moore |

Field programmable gate arrays (FPGAs) are integrated circuits that enable designers to program cust... FPGAs for Dummies - Altera Special Edition
Embedded Design Handbook
by Altera |

The Embedded Design Handbook complements the primary documentation for the Altera® tools for embedd... Embedded Design Handbook
Adam Taylor's MicroZed Chronicles
by Adam Taylor |

This is a collection of a number of blogs I have written for the Xilinx Xcell Daily blog on how to u... Adam Taylor's MicroZed Chronicles
Free Range VHDL
by Bryan Mealy |

The no-frills guide to writing powerful code for you digital implementations.... Free Range VHDL
The Shock and Awe VHDL Tutorial
by Bryan Mealy |

The purpose of this tutorial is to provide students with a guide to help develop the skills necessar... The Shock and Awe VHDL Tutorial
VHDL Tutorial
by Peter J. Ashenden |

The purpose of this tutorial is to describe the modeling language VHDL. VHDL includes facilities for... VHDL Tutorial
VHDL handbook
by Hardi Electronics |

Introduction to Verilog
by Peter M. Nyasulu |

Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated ci... Introduction to Verilog
FPGA Implementation of Digital Filters
by Chi-Jui Chou |

Digital Filtering algorithms are most commonly implemented using general purpose digital signal proc... FPGA Implementation of Digital Filters