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Circuit Design and Simulation with VHDL
Volnei A. Pedroni
Verilog HDL: Digital Design and Modeling
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Designing with FPGAs and CPLDs
Transfering image file to DDR RAM using EDK
by rashmic sent on 2015-01-30 10:31:00
Hi, I am working on Xilinx Spartan 3e Starter kit board which has DDR Ram. I have to transfer ima...
Send a pulse across clocks
by Leo sent on 2015-01-30 03:27:00
Hello, I want to send a pulse from one clock domain to another, knowing tha= t from the time event ...
Where in ISE/Vivado are the chip specific resources listed?
by Svenn sent on 2015-01-29 15:22:00
Hi, I am trying to create a comparison list between various FPGAs in the Xilinx universe. The uni...
Vivado is intensely frustrating
by Rob Gaddi sent on 2015-01-28 14:45:00
So, the following ROM initialization code should be entirely synthesizable. Not so, according to t...
Artix-7 tools, ISE vs Vivado
by Vladimir Ivanov sent on 2015-01-28 03:19:00
Hello, What are the practical pros and cons of using each of ISE or Vivado for the Artix-7 fa...
Xilinx XST and initializing block RAMs
by Christopher Head sent on 2015-01-28 00:49:00
Hi all, I'm using XST 14.2 and trying to use block RAMs to store constant data (i.e. as ROMs) for ...
Instantiating Components or Using Generate statements
by Abdulla873 sent on 2015-01-27 16:08:00
Hi Guys, Are there any differences between instantiating components and using generate statement ...
Why two hold checks done byTimeQuest
by kaz sent on 2015-01-27 14:48:00
Hi, TimeQuest says it uses two hold checks per each setup check. The first hold check for previ...
[RANT] XILINX, Are you freaking kidding me ?
by Simon sent on 2015-01-22 12:54:00
So I wanted to know if it was possible to update an old embedded-developmen= t kit license that's...
Altera Cyclone II
by Michael sent on 2015-01-20 23:46:00
Hi, I have a Altera Cyclone II design where I am looking for a good way to make a complete rese...