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FPGARelated.com has been around since 2006 and has become over the years a very popular resource for Field-programmable gate array (FPGA) experts around the world.
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VHDL Coding Styles and Methodologies
Ben Cohen




Advanced Digital Design with the Verilog(TM) HDL + Xilinx 6.3 Student Edition Package
Michael D. Ciletti




VLSI Digital Signal Processing Systems : Design and Implementation
Keshab K. Parhi




FPGAs: Instant Access
Clive Maxfield




SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
Chris Spear




The Designer's Guide to VHDL
Peter J. Ashenden




Step-by-step Functional Verification with SystemVerilog and OVM
Sasan Iman




FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version
Pong P. Chu




Advanced Digital Design with the Verilog HDL (2nd Edition)
Michael D. Ciletti




VHDL Starter's Guide
Sudhakar Yalamanchili




Save money on (Xilinx,Altera,Microsemi,Lattice,Micron & More
by Stephen Flett sent on 2013-06-20 00:12:00
Attention:
If you buy electronic components and are looking to cut cost.
I work with many ... ![]()
Save Money On (Xilinx,Micron,Altera,Lattice,Microsemi,Quick Logic & more
by Stephen Flett sent on 2013-06-20 00:08:00
Attention:
If you buy electronic components and are looking to cut cost.
Please feel free to con... ![]()
New soft processor core paper publisher?
by Unknown sent on 2013-06-19 17:13:00
I have a general purpose soft processor core that I developed in verilog. =
The processor is unusu... ![]()
comparing between Xilinx and altera
by bjzhangwn@gmail.com sent on 2013-06-19 16:29:00
I have a project that need about 300KLE, I want to choose a device between =
the Xilinx V7 and Alte... ![]()
Modelsim ought to be cheaper
by Kevin Neilson sent on 2013-06-19 14:13:00
Why is Modelsim so expensive? It is a mature product and yet it segfaults =
on me all the time. C... ![]()
Ask about finding maximum and second's maximum number in array is given.
by phanhuyich sent on 2013-06-19 11:40:00
I am starting to study VHDL. Now, I have to do an exercise with the following content:
I have to... ![]()
Chasing Bugs in the Fog
by rickman sent on 2013-06-18 20:24:00
I have a bug in a test fixture that is FPGA based. I had thought it was
in the software which con... ![]()
DDR2 Concurrent Auto Precharge
by Mike Perkins sent on 2013-06-18 12:00:00
I have come across a VHDL Free Model Foundry mt47h16m16.vhd which gives
me some errors.
Has anyo... ![]()
[ANN] LOOPGEN-Fast hardware looping VHDL IPs
by Nikolaos Kavvadias sent on 2013-06-13 06:06:00
The LOOPGEN IP collection provides fast hardware architectures for
implementing nested loop structu... ![]()
problem with the GTX wrapper in questa
by rahulkhikher sent on 2013-06-12 09:34:00
Hi,
Tools used by me : questa - 10.0c , xilinx - 13.2, ubuntu - 11.04.
I am trying to simu... ![]()