Getting Rank of Elements in an Array using VHDL

Started by Md Multan Biswas in comp.arch.fpga1 week ago 1 reply

Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage = [20 40 10 30] ; The...

Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage = [20 40 10 30] ; The position of the elements in the voltage array is ranged from 0 to 3. Using a bubble sorting algorithm, I obtained the position index of the elements in the array as follows: Index (0)= 2 ; Index (1)= 0 ; Index (2)= 3 ; Index (3)= 1 ; However, ba...


All my PDF files suddenly become Chrome HTML Document! Why?

Started by Tianxiang Weng in comp.arch.fpga4 weeks ago 15 replies

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free...

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free Read DC software yesterday? Thank you. Weng


Why Xilinx Ten Gigabit Ethernet PCS/PMA IP Core 32-bit version use less resources than 64-bit version?

Started by Qiu Shui in comp.arch.fpga2 months ago 1 reply

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link...

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link below https://www.xilinx.com/html_docs/ip_docs/pru_files/ten-gig-eth-pcs-pma.html 32-bit version is better in all kinds of aspects of resource utilization. If the 32-bit version has better latency, needs less resource. What's its cost to get these ...


Development tools for Xilinx Spartan 3

Started by Stef in comp.arch.fpga4 months ago 4 replies

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with Modelsim Designer...

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with Modelsim Designer and ISE 9.2, both no longer available. New Vivado versions do not seem to support Spartan 3. What are the current options for making changes to a Spartan 3 design? -- Stef Facts are stubborn, but statistics are more pliable.


Calculation of throughput of sub-block in digital design (I)

Started by Hassan Iqbal in comp.arch.fpga4 months ago

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system. Here...

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system. Here are the few scenarios: 1. DUT takes 10 clock cycles to generate 20 bit output, then another 10 clock cycles to generate the next 20 bit output. -> The maximum throughput is 20 bits per 10 clock cycles = 2 bits/cycle 2. DUT takes 10 clock cycles to ge


Old versions of quartus

Started by Chris Adams in comp.arch.fpga5 months ago 5 replies

Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone know of a mirror or a...

Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone know of a mirror or a way to obtain old versions? You cannot download from the site anymore. Chris


VHDL project. Connecting components to one component

Started by Durko Rurko in comp.arch.fpga5 months ago

Hello guys, I am student at high school interested in VHDL programming and = post quantum algorithms. I have a code where algorithm is divided to...

Hello guys, I am student at high school interested in VHDL programming and = post quantum algorithms. I have a code where algorithm is divided to three = parts. Each part is a component. I would like to create another component, = which will put input to one of those three components, this component will = create output, this will be input to the third component and this one will = create fin...


Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design

Started by Chris Adams in comp.arch.fpga5 months ago 6 replies

Hello, I have a Stratix 10 design that is based around an ip core generated using = Intel's HLS. The core does some simple floating point...

Hello, I have a Stratix 10 design that is based around an ip core generated using = Intel's HLS. The core does some simple floating point operations and by its= elf uses very few resources (1 DSP, a few hundred flops etc). This core sits inside a generate statement like this: generate for(i =3D 0; i < SOMEBIGNUMBER; i=3Di+1) myhlscore u0 (inputs, outputs); ... The de


Is it possible to amplify weak lows and weak highs?

Started by Kevin Simonson in comp.arch.fpga5 months ago 2 replies

I am in possession of a book that says if the gate of an N-channel MOSFET is low (say 0 volts), then the output is high impedance; and that if...

I am in possession of a book that says if the gate of an N-channel MOSFET is low (say 0 volts), then the output is high impedance; and that if that gate is high (say 5 volts), then the voltage at the drain depends on the voltage at the source; if the voltage at the source is low, then the voltage at the drain is low; but if the voltage at the source is high (say 5 volts), then the v


BeMicro Cyclone III 64-bit drivers

Started by Maur Vir in comp.arch.fpga5 months ago 2 replies

I found my old BeMicro Cyclone III board laying around the other day and happen to have a use for it - if I can get it running again. I know it's...

I found my old BeMicro Cyclone III board laying around the other day and happen to have a use for it - if I can get it running again. I know it's an ancient board, but this project doesn't need much, and this old device would be perfect. Unfortunately, none of my current machines are capable of running the drivers that came with it. They are all running either Windows 10 64-bit or 6


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