additional fpga forums

Started by Edward Moore in comp.arch.fpga2 days ago 4 replies

suggestions for alternative fpga-related forums ?

suggestions for alternative fpga-related forums ?


Test Driven Design?

Started by Tim Wescott in comp.arch.fpga1 week ago 47 replies

Anyone doing any test driven design for FPGA work? I've gone over to doing it almost universally for C++ development, because It Just Works...

Anyone doing any test driven design for FPGA work? I've gone over to doing it almost universally for C++ development, because It Just Works -- you lengthen the time to integration a bit, but vastly shorten the actual integration time. I did a web search and didn't find it mentioned -- the traditional "make a test bench" is part way there, but as presented in my textbook* doesn't impo...


Using LUTs to create a phase delayed clock - is it reproducible?

Started by Aleksandar Kuktin in comp.arch.fpga2 weeks ago 4 replies

Hi all, I'm making a system on iCE40 and I've ran out of PLLs. The design incorporates two DDR2 controllers that need to perform several...

Hi all, I'm making a system on iCE40 and I've ran out of PLLs. The design incorporates two DDR2 controllers that need to perform several operations delayed with respect to the system clock. I'm gonna use a phase delayed clock for that. So my approach is to take the clock signal and pipe it through several LUTs, thus delaying it. But - how comparable are LUT delays between differen...


Digital-to-Analog Converter LTC 2624, Spartan-3A

Started by m m in comp.arch.fpga3 weeks ago 9 replies

I would like to know if anyone here has already done a VHDL code to communicate/give commands to the LTC2624 Digital to Analog Converter that...

I would like to know if anyone here has already done a VHDL code to communicate/give commands to the LTC2624 Digital to Analog Converter that has the Spartan-3A starterkit board. I am not asking for the code specifically, but I would like your feedback regarding to this problem: I've a code, which in simulation seems to be all ok, all the timings are met according to the timing specifi...


graphics for FPGA design

Started by john in comp.arch.fpga3 weeks ago 1 reply

does anyone have a set of symbols that can help with fpga documentation? (Something for dia perhaps or coreldraw maybe) preferably not...

does anyone have a set of symbols that can help with fpga documentation? (Something for dia perhaps or coreldraw maybe) preferably not visio Or does everyone do this manually all the time? Clearly it's not that complex but what do you all use? -- john ========================= http://johntech.co.uk =========================


Beginer's FPGA with SERDES

Started by rickman in comp.arch.fpga1 month ago 10 replies

Some hams want to work with FPGAs to generate high speed PN sequences in the GHz range. LFSR designs are about as simple as you can get in an...

Some hams want to work with FPGAs to generate high speed PN sequences in the GHz range. LFSR designs are about as simple as you can get in an FPGA. The only trick is getting the resulting signal out of the FPGA. Rather than outputting a parallel word at some 100's of MHz into a shift register clocked in the GHz range, it seems easier to use a SERDES to shift it out directly from the F...


Request for an example in Verilog

Started by Bitan Mallik in comp.arch.fpga1 month ago

Dear All, I am a student with primitive experience in verilog. I have a small verific= ation task for a top module. I have simplified the task...

Dear All, I am a student with primitive experience in verilog. I have a small verific= ation task for a top module. I have simplified the task in the below descri= ption, so that you can give me a quick response. There could be solve for t= his problem in various ways. But ideally I am finding a solution to create = an automatic test setup. Please find below the problem. If you could wri...


UART receiver

Started by promach in comp.arch.fpga1 month ago 1 reply

Hi, I am working on UART receiver. As of now, I am stucked at http://paste.ubuntu.com/25720292/ I could not find a proper hardware writing style...

Hi, I am working on UART receiver. As of now, I am stucked at http://paste.ubuntu.com/25720292/ I could not find a proper hardware writing style to continue with line 14 the overall hierarchy : https://i.imgur.com/lVEtKXT.png module sampling_strobe_generator(clk, start_detected, sampling_strobe); // produces sampling signal for the incoming Rx input clk, start_detected; output r...


Artix-7 boards

Started by john in comp.arch.fpga2 months ago 2 replies

Has anyone had any experience of using these...

Has anyone had any experience of using these : http://www.robotshop.com/uk/cmod-a7-35t-breadboardable-artix-7-fpga-module.ht ml?gclid=EAIaIQobChMIkqXI9rje1gIVxZkbCh2l_AkhEAEYASAAEgLo_PD_BwE They aren't in stock yet but maybe some have been shipped. I'm looking for comments on them for use with novice FPGA users. Anything you have to say may be helpful as I'm looking to buy a few of them....


Xilinx Platform cable USB and impact on linux without windrvr

Started by Michael Gernoth in comp.arch.fpga2 months ago 23 replies

Hello, after being bitten by windrvr once again (it did not compile after a kernel upgrade), I decided to see if I could get the Xilinx USB...

Hello, after being bitten by windrvr once again (it did not compile after a kernel upgrade), I decided to see if I could get the Xilinx USB cable and impact working without a kernel module. To achieve this, I have written a wrapper library for impact which maps calls to windrvr to the userspace libusb-library which should be available on all modern linux distributions. With this wrapper I...


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