No judgment, just forgiveness and guidance

Started by Rick C. Hodgin in comp.arch.fpga52 minutes ago 12 replies

We all have sin. Sin places us under judgment and separates us from God. Sin is the embracing of things which run contrary to the way...

We all have sin. Sin places us under judgment and separates us from God. Sin is the embracing of things which run contrary to the way our universe was designed. It is therefore a type of cancer against creation, eating away at what was given us by God, eating away at what's right, true, and proper, all of the things which lead to our natural love and growth as God intended. Jesus came t...


Test Driven Design?

Started by Tim Wescott in comp.arch.fpga3 days ago 41 replies

Anyone doing any test driven design for FPGA work? I've gone over to doing it almost universally for C++ development, because It Just Works...

Anyone doing any test driven design for FPGA work? I've gone over to doing it almost universally for C++ development, because It Just Works -- you lengthen the time to integration a bit, but vastly shorten the actual integration time. I did a web search and didn't find it mentioned -- the traditional "make a test bench" is part way there, but as presented in my textbook* doesn't impo...


Spartan 6 Digital controlled oscillator

Started by john tra in comp.arch.fpga5 days ago 2 replies

Hello, What is the best way to implement a 30 MHz clock generation circuit that can be dynamically controlled to provide fine frequency...

Hello, What is the best way to implement a 30 MHz clock generation circuit that can be dynamically controlled to provide fine frequency offsets in a Spartan 6, the clock is to be used internally and output via a pin? Would a DCM provide the functionality and what would the minimum frequency increment be? Thanks John


Configuration fault recovery

Started by Yannick Lamarre in comp.arch.fpga5 days ago 4 replies

Hi all, I've been thinking about this problem for a while and shared it with a few colleagues, but no one has yet to come up with an answer. For...

Hi all, I've been thinking about this problem for a while and shared it with a few colleagues, but no one has yet to come up with an answer. For some configuration, an FPGA can be configured so that two different drivers are connected on that same line internally. A practical example would be two BUFGs driving the same line on a Spartan6. If those two drivers are driving a different value in a ...


Pipelining on Multiple Clock Edges

Started by rickman in comp.arch.fpga1 week ago 8 replies

I recall a processor implementation where the guy tried to say that one particular part of the pipeline design had a register inserted which was...

I recall a processor implementation where the guy tried to say that one particular part of the pipeline design had a register inserted which was clocked on the negative edge. I could never see how this would positively impact anything. In fact, the setup and hold time of the register, not to mention the routing time, would add to the delay in that pipeline stage. Was I missing somet...


increment or decrement one of 16, 16-bit registers

Started by Tim Wescott in comp.arch.fpga1 week ago 22 replies

I've been geeking out on the COSMAC 1802 lately -- it was the first processor that I owned all just for me, and that I wrote programs for (in...

I've been geeking out on the COSMAC 1802 lately -- it was the first processor that I owned all just for me, and that I wrote programs for (in machine code -- not assembly). One of the features of this chip is that while the usual ALU is 8-bit and centered around memory fetches and the accumulator (which they call the 'D' register), there's a 16 x 16-bit register file. Any one of these ...


size lattice iCE40 config files

Started by kristoff in comp.arch.fpga2 weeks ago 2 replies

Hi all, I am working on a STM32-based programmer for the olimex iCE40HX1K-EVB fpga dev.board. (now trying to implement the "SPI Slave...

Hi all, I am working on a STM32-based programmer for the olimex iCE40HX1K-EVB fpga dev.board. (now trying to implement the "SPI Slave configuration" protocol). Looking at the Lattice "programming and Configuration guide" (page 11), it is noted on table 8 that a FLASH EPROM for a ICE40-LP/LX1K must be at least 34112 bytes. However, all binary-files as created by the icestorm-tools...


Lattice iCE40 UltraLite DIPSY - what happened?

Started by rickman in comp.arch.fpga2 weeks ago 6 replies

I was digging around for info on the iCE40 UL and found info on the DIPSY from 2015 when it was breaking news. Not sure how I missed it, but...

I was digging around for info on the iCE40 UL and found info on the DIPSY from 2015 when it was breaking news. Not sure how I missed it, but this is a very small unit with a very tiny FPGA (likely the smallest FPGA package ever - 2 mm^2) and an LDO for the core power and of course some connectors. I found a github page with various design details and an Indiegogo page. There I foun...


glitching AND gate

Started by David Bridgham in comp.arch.fpga2 weeks ago 25 replies

I have a question about how FPGAs handle signals into combinational logic. I have following setup: always @(posedge interrupt_check)...

I have a question about how FPGAs handle signals into combinational logic. I have following setup: always @(posedge interrupt_check) interrupt_detect


RISC-V Support in FPGA

Started by rickman in comp.arch.fpga2 weeks ago 62 replies

I don't recall where, but there was a conversation recently about using the RISC-V in FPGAs. Thought I'd pass on the...

I don't recall where, but there was a conversation recently about using the RISC-V in FPGAs. Thought I'd pass on the link. https://www.microsemi.com/products/fpga-soc/technology-solutions/embedded-processing/risc-v -- Rick C


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