Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone know of a mirror or a...

Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone know of a mirror or a way to obtain old versions? You cannot download from the site anymore. Chris

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free...

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free Read DC software yesterday? Thank you. Weng

A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my...

A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my customer has said "no" to the 100% Chinese brand... US government customers, ya know! So now I'm looking at a BGA. I don't want to get into fine PCB design rules, so 1.0 mm ball pitch is my preference. The only devices I can find tha

I have noticed, that the categories on the list of projects https://opencores.org/projects do not unfold after clicking. That makes browsing...

I have noticed, that the categories on the list of projects https://opencores.org/projects do not unfold after clicking. That makes browsing projects impossible. Is it a problem with my browser (Firefox on Linux) or with the website? Regards, Wojtek

Excess 3 Adder: Add 2 three digits numbers in excess 3. ex. 998+345 in excess 3. i don't have any idea on how to continue, please help. thx...

Excess 3 Adder: Add 2 three digits numbers in excess 3. ex. 998+345 in excess 3. i don't have any idea on how to continue, please help. thx ! module Decimal_to_E3(input[10:0] dec, output reg[15:0] E3); reg[10:0] aux; reg[1:0] counter; always @ (dec) begin aux = dec; E3 = {4{4'b0011}}; counter = 2'b00; while(aux != 0) begin E3[counter * 4 +: 4] = aux % 10 + 3; aux = aux / 10; coun...

Hello All,=20 I'm just getting started with Verilog.=20 I created the following Programs Counter for a simple Stack Machine.=20 The PC is an...

Hello All,=20 I'm just getting started with Verilog.=20 I created the following Programs Counter for a simple Stack Machine.=20 The PC is an 8-bit register that stores the address of the command being e= xecuted. The clock pulse at the positive edge of the clock signal (except mode =3D 2= ). If mode =3D 0 reset PC to 0 If mode =3D 1, set the PC value to be equal to the value in the data...

[This is a repost. Posted this to comp.lang.vhdl a few days ago, but no replies. So maybe nobody knows the answer, it was a malformed...

[This is a repost. Posted this to comp.lang.vhdl a few days ago, but no replies. So maybe nobody knows the answer, it was a malformed question or there are no readers in that group. So a repost (with a little clarification, I hope) with the comp.arch.fpga added at least resolves the last option. ;-)] It has been a while since I used VHDL so I am a little rusty. Did not much use the gener...

Suppose we read in an FPGA bitstream file as 16-bit words, and want to output a compressed file, to save room in a small flash chip. If an...

Suppose we read in an FPGA bitstream file as 16-bit words, and want to output a compressed file, to save room in a small flash chip. If an input word is 0000, output a single 0 bit to the compressed file. If a word is nonzero, output a 1 followed by that 16-bit word. The decompressor will be very simple. I wrote a little PowerBasic program to test the compression, the input being ...

https://t.co/4xQ8CXBhmm

https://t.co/4xQ8CXBhmm

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic...

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic is compiled? Would a simple application use less? Are the streams very compressible? We have done some simple run-length coding to greatly reduce the storage requirement for other FPGAs. Configs tend to have long runs of 0's. The T20/256 claims...