Mod-24: The State of High-Level Synthesis in 2016

Started by Kevin Neilson in comp.arch.fpga21 hours ago 7 replies

It's 2016 and I still have to write out most of my code at very low levels of abstraction like I did ten years ago. Whenever I hear about a new...

It's 2016 and I still have to write out most of my code at very low levels of abstraction like I did ten years ago. Whenever I hear about a new tool that supposedly converts C to gates, I don't even look into it, because I can't even get Verilog to synth properly. My latest example: I needed to reduce an 12-bit number, mod-24. input [11:0] x; always@(posedge clk) xmod24


Lattice Diamond 3.7 and Synplify

Started by rickman in comp.arch.fpga3 days ago 3 replies

I am trying to run the latest version of Lattice Diamond free edition. When I attempt to synthesize through the Diamond GUI I get "error code...

I am trying to run the latest version of Lattice Diamond free edition. When I attempt to synthesize through the Diamond GUI I get "error code 3". I've opened a ticket with Lattice support but after 2 weeks I am not getting anywhere with them. If there isn't something simple wrong with my project, they can't seem to be of much help and take two days to respond to every comment I make. ...


Lattice MachXO2 breakout board - replacing FPGA with different one ?

Started by Brane2 in comp.arch.fpga2 weeks ago 3 replies

Hi, I have a couple of that neat boards with XO2-7000 and not much else. I managed to burn the FPGA on one of them and since Farnell didn't...

Hi, I have a couple of that neat boards with XO2-7000 and not much else. I managed to burn the FPGA on one of them and since Farnell didn't have the exact 7000HE model that was on the board, I used 7000HC and bridged VCC so that chips gets 3.3V for core power that it wants. But now I can't program it through FTDI. I've noticed several variations of the board. Some had XO2-1200 while mine ...


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Started by Nicholas Randall Forystek in comp.arch.fpga2 weeks ago

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Lattice Diamond and VHDL-2008

Started by rickman in comp.arch.fpga2 weeks ago 6 replies

I don't have any trouble getting the simulation (Active HDL) or synthesis (Synplify) tools to work with VHDL-2008, but the Lattice tool itself...

I don't have any trouble getting the simulation (Active HDL) or synthesis (Synplify) tools to work with VHDL-2008, but the Lattice tool itself doesn't seem to understand it. When Diamond analyzes the source files it complains of syntax errors. The rest of the tool seems to work just fine and this doesn't stop me from completing the project. I did an Internet search and found a post at...


need some help with altera quartus

Started by kristoff in comp.arch.fpga2 weeks ago 4 replies

Hi all, To learn VHDL and FPGAs, I bought a number of boards, one of them being this one:...

Hi all, To learn VHDL and FPGAs, I bought a number of boards, one of them being this one: http://www.aliexpress.com/item/EP4CE10-altera-fpga-board-fpga-development-board-fpga-altera-boar d-fpga-development-board/32637947021.html It's a Altera cyclone IV with 16 Mbit of serial flash (M25P16/EPSC16) to store the configuration file. Next to that, I have a USB Blaster. Now, I am


Problem with Lattice Diamond IPExpress software.

Started by Cecil Bayona in comp.arch.fpga4 weeks ago

Not sure what to make of this problem, I am having IPexpress in Lattice Diamond generate a corrupted file if I define a RAM module for use with...

Not sure what to make of this problem, I am having IPexpress in Lattice Diamond generate a corrupted file if I define a RAM module for use with a soft CPU. I have a copy of the original generated file, but when I try to generate myself following the documentation, the file generated differs from the original by two words in the area of loading data into the RAM. I have three soft CPUs...


J1 forth processor in FPGA - possibility of interactive work?

Started by wzab in comp.arch.fpga4 weeks ago 35 replies

Hi, I'm very impressed with a J1 forth processor: http://excamera.com/sphinx/fpga-j1.html I'd like to use it to implement simple non-time...

Hi, I'm very impressed with a J1 forth processor: http://excamera.com/sphinx/fpga-j1.html I'd like to use it to implement simple non-time critical control and debugging layer in my FPGA based DSP system. However to accomplish it I need to add possibility of interactive work via console connected either by UART or by JTAG. Has anybody tried to extend the J1 published in http://excamera.co...


Active HDL Generic Controls

Started by rickman in comp.arch.fpga1 month ago 5 replies

I am working with Active HDL and I'm pretty sure in the past I was able to set generics at the top level from within the simulator. I see in...

I am working with Active HDL and I'm pretty sure in the past I was able to set generics at the top level from within the simulator. I see in the Design, Settings dialog box they have a Simulation, Generic/Parameters choice which looks like it should display design generics, but I can't see them. The help file talks about editing these items, but I see no editing controls either. Any...


Advice to a newbie

Started by Cecil Bayona in comp.arch.fpga1 month ago 53 replies

I a retired person with limited resources and I've always been interested in CPU design, so now that I have time I wanted to give it a go...

I a retired person with limited resources and I've always been interested in CPU design, so now that I have time I wanted to give it a go using FPGAs to design simple CPUs. I would like some advice on several topics, one being which HDL language to learn first, although Verilog seems simpler I've read articles that encourages beginners to start with VHDL, although it seems more wordy, I...


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