Intel (Altera) announces Cyclone-10

Started by GaborSzakacs in comp.arch.fpga19 hours ago 11 replies

It looks like Intel has learned to count from Microsoft. The previous generation of Cyclone was...

It looks like Intel has learned to count from Microsoft. The previous generation of Cyclone was Cyclone-5. https://www.altera.com/products/fpga/cyclone-series/cyclone-10.html -- Gabor


Plan to go to church Sunday

Started by Rick C. Hodgin in comp.arch.fpga1 day ago 1 reply

This message is for those who have a drawing from within to do so. I want you to know that drawing is from God. He is reaching out to you to...

This message is for those who have a drawing from within to do so. I want you to know that drawing is from God. He is reaching out to you to save your eternal soul from the judgment for sin. If you hear His call on the inside, then go to church on Sunday. Seek to learn more about this drawing, why it exists, and what it means to you. You know that have sinned. You know that you need t...


cmos delay vs temperature

Started by John Larkin in comp.arch.fpga2 days ago 3 replies

I found one old Fairchild appnote that has some numbers https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/CMOS_Delay_Temp.pdf which...

I found one old Fairchild appnote that has some numbers https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/CMOS_Delay_Temp.pdf which averages to around +3000 ppm/degC, or about +3 ps per ns of prop delay per degree C. That's with 50 pF loading, sorta high. This is HC, pretty old technology. I have a vague impression that the innards of a typical FPGA may be better. Here's a ri...


CFP: The International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE)

Started by allconferencecfplaerts ShareURL in comp.arch.fpga2 days ago

The International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE) ...

The International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE) ISSN : 2394 - 0816 Call for papers *************** The International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE) is an open access peer-reviewed journal...


All-real FFT for FPGA

Started by Tim Wescott in comp.arch.fpga4 days ago 34 replies

So, there are algorithms out there to perform an FFT on real data, that save (I think) roughly 2x the calculations of FFTs for complex...

So, there are algorithms out there to perform an FFT on real data, that save (I think) roughly 2x the calculations of FFTs for complex data. I did a quick search, but didn't find any that are made specifically for FPGAs. Was my search too quick, or are there no IP sources to do this? It would seem like a slam-dunk for Xilinx and Intel/Altera to include these algorithms in their FFT li...


Go to church

Started by Rick C. Hodgin in comp.arch.fpga1 week ago

That still small voice you hear on the inside, the one drawing you from within, reminding you of the things you should be doing, and pointing...

That still small voice you hear on the inside, the one drawing you from within, reminding you of the things you should be doing, and pointing out the things you shouldn't be doing ... listen to it. That voice was put there by God to guide you into all rightness, and away from everything wrong, hurtful and harmful (to yourself and others). Even though you've done hurtful and harmful th...


Anyone use 1's compliment or signed magnitude?

Started by Tim Wescott in comp.arch.fpga2 weeks ago 18 replies

This is kind of a survey; I need some perspective (possibly historical) Are there any digital systems that you know of that use 1's compliment...

This is kind of a survey; I need some perspective (possibly historical) Are there any digital systems that you know of that use 1's compliment or signed-magnitude number representation for technical reasons? Have you ever used it in the past? Is the world down to legacy applications and interfacing with legacy sensors? TIA. -- Tim Wescott Wescott Design Services http://w...


VHDL, how to convert sensor data to Q15

Started by Anonymous in comp.arch.fpga2 weeks ago 13 replies

Sensor data length is 16 bit data, value is from -32768 to 32767,i think data format represented as one highest is sign and others are integers,...

Sensor data length is 16 bit data, value is from -32768 to 32767,i think data format represented as one highest is sign and others are integers, who can help how to convert it to Q15 data format in VHDL? Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and others are fractional from -1 to 1 Sensor is ADC output is 16 bit format, one sign and other integer so it need only...


VHDL Editors (esp. V3S)

Started by Anonymous in comp.arch.fpga2 weeks ago 14 replies

As X and A's integrated editors are more or less limited, I guess many people will looking for better alternatives. The usual suspects will be...

As X and A's integrated editors are more or less limited, I guess many people will looking for better alternatives. The usual suspects will be Emacs (with VHDL mode) and Sigasi. For me personally, I never really liked Emacs and found Sigasi just a bit too expensive. So some time ago I came across V3S from www.vide-software.at. It is a quite powerful and fair priced VHDL plug-in f


Why study the Bible? What can we learn?

Started by Rick C. Hodgin in comp.arch.fpga2 weeks ago 1 reply

What is a Christian teaching like? It's all summed up from the realization: Christ's righteousness given to us, our sin given to Him ...

What is a Christian teaching like? It's all summed up from the realization: Christ's righteousness given to us, our sin given to Him https://twitter.com/DrStevenJLawson/status/826879446254809090 There cannot be better news than that. It is the gospel (the "good news"): The word "gospel" is Strong's 2098, euaggelion: http://biblehub.com/greek/2098.htm Short Defin...


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