All my PDF files suddenly become Chrome HTML Document! Why?

Started by Tianxiang Weng in comp.arch.fpga2 weeks ago 9 replies

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free...

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free Read DC software yesterday? Thank you. Weng


Is it possible to amplify weak lows and weak highs?

Started by Kevin Simonson in comp.arch.fpga2 weeks ago 1 reply

I am in possession of a book that says if the gate of an N-channel MOSFET is low (say 0 volts), then the output is high impedance; and that if...

I am in possession of a book that says if the gate of an N-channel MOSFET is low (say 0 volts), then the output is high impedance; and that if that gate is high (say 5 volts), then the voltage at the drain depends on the voltage at the source; if the voltage at the source is low, then the voltage at the drain is low; but if the voltage at the source is high (say 5 volts), then the v


How to Implement a Random Access Memory at the Transistor Level

Started by Kevin Simonson in comp.arch.fpga3 weeks ago 2 replies

I don't know if this is the right forum to post this to. If there's a forum= that would be more appropriate for a question like this, please let...

I don't know if this is the right forum to post this to. If there's a forum= that would be more appropriate for a question like this, please let me kno= w. Let's say for a moment that I need to build a Random Access Memory that con= sists of 256 nybbles. An eight-bit address bus and a four-bit data bus conn= ect the CPU to each of the 256 nybbles. To make things simple, let's assume= tha...


Xilinx forums have disappeared?

Started by Wojciech Zabolotny in comp.arch.fpga1 month ago 10 replies

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally...

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally redirected to https://support.xilinx.com/s/ . There is no forum available any more. Does it mean that all the knowledge created by the users is lost forever? If I remember it happened once in the past with Xilinx forum. Have they done it again? Reg...


Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design

Started by Chris Adams in comp.arch.fpga1 month ago 4 replies

Hello, I have a Stratix 10 design that is based around an ip core generated using = Intel's HLS. The core does some simple floating point...

Hello, I have a Stratix 10 design that is based around an ip core generated using = Intel's HLS. The core does some simple floating point operations and by its= elf uses very few resources (1 DSP, a few hundred flops etc). This core sits inside a generate statement like this: generate for(i =3D 0; i < SOMEBIGNUMBER; i=3Di+1) myhlscore u0 (inputs, outputs); ... The de


Verilog HDL Finite State Machine - detecting a decimal number

Started by Tanishk Singh in comp.arch.fpga2 months ago 1 reply

Hi all, I am trying to build a sequence detector to detect a decimal number like 10= 92 when a stream of numbers from 0-9 is given as input....

Hi all, I am trying to build a sequence detector to detect a decimal number like 10= 92 when a stream of numbers from 0-9 is given as input. Do you think just c= hanging the width of input i.e parallel inputs instead of series would resu= lt in pattern detection? I am lost in this, please help. If you have any re= sources around this do share them.


Is there any software I can use to transform state machines in VHDL into drawings?

Started by Tianxiang Weng in comp.arch.fpga2 months ago 7 replies

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is...

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is there any software I can use to transform state machines in VHDL into drawings? Thank you. Weng


UDP -FPGA point to point

Started by Manav Nair in comp.arch.fpga3 months ago 3 replies

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between...

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between the PC and the FPGA. The communication is happening point to point so I was wondering do I need ARP implementation in my stack or can I just broadcast the message. I am building a UDP stack but was wondering is ARP a necessary requirement. Also, the ...


Notepad++ is an excellent editor for coding VHDL

Started by Tianxiang Weng in comp.arch.fpga4 months ago 1 reply

Hi, In the working process for my private project, I use free Notepad++ to code VHDL code and appreciate it very much! Here is an example of...

Hi, In the working process for my private project, I use free Notepad++ to code VHDL code and appreciate it very much! Here is an example of how powerful Notepad++ is: In 27 files, I easily found that I use the statement "when others => null; " 119 times and the statement "end case;" 117 times. There are certainly 2 mismatches for the 2 types of statements. I found only 1 mismat


GDB from my university...

Started by Yousaf tehseen in comp.arch.fpga5 months ago 2 replies

CS302 – Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counter. The stated...

CS302 – Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counter. The stated PAL can be programmed using ABEL (Advanced Boolean Expression Language) and VHDL (Verilog Hardware Descriptive Language). Which programming technology would you use to accomplish the task outlined considering the constraints given below?


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