FPGA sensitivities

Started by John Larkin in comp.arch.fpga3 weeks ago 4 replies

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs...

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs some voltages: 1.8 aux no measurable DC effect 3.3 vccio no measurable DC effect 2.5 vccio ditto (key io's are LVDS in this bank) +1 core -10 ps per millivolt! If I vary the trigger frequency, I can see the delay heterodyning against the 1....


What is wrong with low level code?

Started by Kevin Simonson in comp.arch.fpga3 weeks ago 3 replies

I recently posted a Verilog module to this forum, and someone responded that I was coding at a very low level, which was true; I was referring to...

I recently posted a Verilog module to this forum, and someone responded that I was coding at a very low level, which was true; I was referring to XOR gates, NAND gates, NOR gates, and NOT gates. Is there something wrong with writing my code at such a low level? If I have a fairly good understanding of how my algorithm needs to run at such a low level, then what is wrong with writing


Piplineing logic alot? I have a tool for you

Started by Julian Kemmerer in comp.arch.fpga4 weeks ago

Try out the PipelineC compiler - it pipelines combinatorial logic for you. https://github.com/JulianKemmerer/PipelineC/wiki It is also a...

Try out the PipelineC compiler - it pipelines combinatorial logic for you. https://github.com/JulianKemmerer/PipelineC/wiki It is also a full hardware description language - thats cool. Looking for folks interested in using or contributing to the project. I need some compiler help :) Super happy to answer questions - thanks folks!


Multi-FPGA Interconnection: latest techniques

Started by partha sarathy in comp.arch.fpga4 weeks ago 9 replies

Hi Experts, In FPGA Prototyping/Emulation flows, Multi-FPGA partitioning puts limitation on performance due to limited IO pins. What are the...

Hi Experts, In FPGA Prototyping/Emulation flows, Multi-FPGA partitioning puts limitation on performance due to limited IO pins. What are the latest Multi-FPGA Interconnection techniques available today? By using Multi Gigabit Transceivers , how much performance improvement is expected ? Thanks in Advance Parth


How powerful is Verilog at using parameters to specify designs?

Started by Kevin Simonson in comp.arch.fpga4 weeks ago 21 replies

I have a design in mind that would fit in this skeleton: [code] module xyz ( result, leftOp, rightOp); parameter integer nmBits =...

I have a design in mind that would fit in this skeleton: [code] module xyz ( result, leftOp, rightOp); parameter integer nmBits = 1; localparam integer highBit = nmBits - 1; output result; input [ highBit:0] leftOp; input [ highBit:0] rightOp; // ... endmodule [/code] The way (xyz) is designed, this module would work differently for different values of (nmBits),


Active HDL Entity Retention

Started by Rick C in comp.arch.fpga4 weeks ago 4 replies

I have multiple entities in a file. I renamed one of them. The design bro= wser now shows both the old entity and the new one. It won't allow...

I have multiple entities in a file. I renamed one of them. The design bro= wser now shows both the old entity and the new one. It won't allow me to d= o anything with the old entity like delete it. The name of the old entity = no longer shows up anywhere in the file. Any idea how to get rid of this p= hantom entity? =20 I finally tried deleting the library and recompiling which seems t...


Is there any way to get a different font for code sections?

Started by Kevin Simonson in comp.arch.fpga1 month ago 1 reply

When I make posts to this forum and have code to show, I do something like = this: [code] module xyz (); // ... endmodule [/code] This...

When I make posts to this forum and have code to show, I do something like = this: [code] module xyz (); // ... endmodule [/code] This has worked on other forums, creating a window with the text in a diffe= rent font for whatever was enclosed between the [code] and [/code] tags, bu= t it doesn't look like it works here. Is there any way to get my code repre= sented differently in thi...


Exponential Regression by XSG

Started by Mjzoob I. Ibrahim in comp.arch.fpga1 month ago

I want to perform an exponential regression function by using the Xilinx system generator. To support fixed-point data, 12 bit, and 1 MSPS. That...

I want to perform an exponential regression function by using the Xilinx system generator. To support fixed-point data, 12 bit, and 1 MSPS. That to estimate a logarithmic increase and decrease the detector signal. Thanks for your help


Gowin FPGA Oddities

Started by Rick C in comp.arch.fpga1 month ago 27 replies

Gowin seems to have some nice configuration modes in their parts. Of course they have an auto boot from internal flash and JTAG can be used to...

Gowin seems to have some nice configuration modes in their parts. Of course they have an auto boot from internal flash and JTAG can be used to program either the RAM or the Flash. They also have master and slave SPI modes, a serial mode that daisy chains multiple FPGAs and a parallel bus mode along with a mode to try reading external flash and fall back to internal auto boot. But


exponential regression in XSG

Started by Mjzoob I. Ibrahim in comp.arch.fpga1 month ago 1 reply

Hi Guys, I hope everybody is fine. I would like to perform an exponential regression function by using the Xilinx system generator. could you...

Hi Guys, I hope everybody is fine. I would like to perform an exponential regression function by using the Xilinx system generator. could you please make help me. thanks and regards M. I. Ibrahim


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