Tiny CPUs for Slow Logic

Started by Anonymous in comp.arch.fpga31 minutes ago 21 replies

Most of us have implemented small processors for logic operations that don't need to happen at high speed. Simple CPUs can be built into an FPGA...

Most of us have implemented small processors for logic operations that don't need to happen at high speed. Simple CPUs can be built into an FPGA using a very small footprint much like the ALU blocks. There are stack based processors that are very small, smaller than even a few kB of memory. If they were easily programmable in something other than C would anyone be interested?


Color sensor with BASYS3 VHDL

Started by Anonymous in comp.arch.fpga22 hours ago 1 reply

Hi, I need to make a circuit which does the following thing: When it sees a red object it will send output 0 until it sees a green objec= t...

Hi, I need to make a circuit which does the following thing: When it sees a red object it will send output 0 until it sees a green objec= t (like a well colored cubic toy), after it sees green it will send output = 1 until it sees red again. ( If it is hard to implement I'm ok with just ou= tput 0 when it sees red and outputs 1 when it sees green, I mean it is ok i= f the outputs not contin...


Anyone have files from the old Xilinx FTP?

Started by Tim Regeant in comp.arch.fpga4 days ago 5 replies

Hi all, Looking for someone who has FTP files from 1997 for the XACT Foundation v6.0.2 update. Web Archive has the files listed here:...

Hi all, Looking for someone who has FTP files from 1997 for the XACT Foundation v6.0.2 update. Web Archive has the files listed here: https://web.archive.org/web/19970616112705/http://www.xilinx.com/support/techsup/ftp/htm_index/s w_foundation.htm Anyone capture these files? Thanks.


Implementation of Modbus Slave using only FPGA, without any softcore

Started by Swapnil Patil in comp.arch.fpga5 days ago 9 replies

Hello Folks, I wanted to Implement Modbus Slave protocol with the use of only FPGA, without use of any external or internal softcore,Hardcore....

Hello Folks, I wanted to Implement Modbus Slave protocol with the use of only FPGA, without use of any external or internal softcore,Hardcore. Currently i have successfully Implemented Modbus Master protcol, Now I am Looking forward to bulit Modbus Slave as well. For Implementation Of Modbus Slave I am currently using Spartan6 FPGA and ISE 14.7 for For coding In VHDl. I want some hel...


Green/Red detector and button controlled car (BASYS3/VHDL)

Started by Anonymous in comp.arch.fpga6 days ago

Hi, I am a 2nd-year ee student, and I need to make a term Project. With BASYS3 by using VHDL. My purpose is constructing a car which can be...

Hi, I am a 2nd-year ee student, and I need to make a term Project. With BASYS3 by using VHDL. My purpose is constructing a car which can be controlled with the buttons on BASYS3 ( I think I need Bluetooth module for it to RC a car). In addition to that my car should stop when it sees red ( i think I should use a color sensor for it) and should not work until it sees a green. These


Cyclone V decimation

Started by Piotr Wyderski in comp.arch.fpga3 weeks ago 14 replies

Hi, the input signal is 14 bits signed@750ksps. I would like to decimate it by a modest factor of ~3000. What would be the best way of doing...

Hi, the input signal is 14 bits signed@750ksps. I would like to decimate it by a modest factor of ~3000. What would be the best way of doing it on a Cyclone V, resource-wise? My usual approach would be a cascade of CIC decimators followed by a FIR corrector, but since there are the DSP blocks, I don't feel it to be the "right" (albeit correct) approach. I'm new to the V family and lack...


Altera Cyclone replacement

Started by Stef in comp.arch.fpga1 month ago 36 replies

Hi, We got an old design with an Altera Cyclone FPGA (EP1C12F324). These are probably obsolete (Can't find any info on them on the...

Hi, We got an old design with an Altera Cyclone FPGA (EP1C12F324). These are probably obsolete (Can't find any info on them on the Intel site, Farnell is out of stock, etc.). Currently active are the Cyclone-IV and Cyclone-V if I understood correctly. Is a design from a Cyclone portable to a Cyclone-IV/V? What kind of changes should I expect to code and board? Design includes NIOS. Or...


MachXO2 internal clock tolerance / accuracy

Started by tcz2008 in comp.arch.fpga1 month ago 1 reply

Hi everyone! I have a hard time finding the tolerance / accuracy for the internal oscillator for the MachXO2. I seem to remember it being...

Hi everyone! I have a hard time finding the tolerance / accuracy for the internal oscillator for the MachXO2. I seem to remember it being around 5%, which isn't really that great. Can anyone point me in the direction where that's definitively mentioned?! Cheers! -Mux


Is it possible to implement Ethernet on bare metal FPGA, Without Use of any Hard or Soft core processor?

Started by Swapnil Patil in comp.arch.fpga1 month ago 46 replies

Hello folks, Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? I don't want to...

Hello folks, Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? I don't want to connect any Hard or Soft core processor. also I have looked into WIZnet W5300 Ethernet controller interfacing to spartan 6, but I don't want to connect any such controller just spartan 6. So how can it be done? It is not necessary to use spartan 6 b...


Testing (please ignore)

Started by A.P.Richelieu in comp.arch.fpga1 month ago

Please ignore

Please ignore


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