Altera USB Blaster clone driver for STM32F1xx

Started by Jim Horn in comp.arch.fpga1 day ago 1 reply

Does anyone have the drivers for Windows 10 64 bit use of the STM32F1xx based USB Blaster clones? They are readily available, inexpensive and the...

Does anyone have the drivers for Windows 10 64 bit use of the STM32F1xx based USB Blaster clones? They are readily available, inexpensive and the STM32 Cortex CPU should have plenty of performance for these to work well. However, the firmware isn't fully Altera compatible so when connected via USB they crash the machine with a blue screen reboot. I just received mine and for the pri


Zero Address CPU logic

Started by Cecil Bayona in comp.arch.fpga2 days ago 3 replies

On 8/29/2016 7:55 PM, rickman wrote: > On 8/29/2016 4:30 PM, Cecil Bayona wrote: > > Nothing Fancy, that is why in my earlier post I...

On 8/29/2016 7:55 PM, rickman wrote: > On 8/29/2016 4:30 PM, Cecil Bayona wrote: > > Nothing Fancy, that is why in my earlier post I mentioned that I don't > > have a lot of experience. I been working a 32 bit stack based CPU, but > > it's a work in progress, I'm still sorting it out, it taken less than > > 20% of the chip, but a stack CPU are rather simple compared to other > > CPU's, whe


Help me choose an FPGA to design network protocols

Started by PM X in comp.arch.fpga2 days ago 19 replies

Hi all, I have over a decade of experience in hardware design, but almost all of it= is in ASIC. I had done some FPGA projects in school, but...

Hi all, I have over a decade of experience in hardware design, but almost all of it= is in ASIC. I had done some FPGA projects in school, but nothing after tha= t. So after all these years, I want to work on some personal FPGA projects = (mainly to prepare myself for future job interviews). I have the following = two questions. 1. What is an FPGA board that I can buy for this purpose? I a...


Need help finding Synario Futurenet 6.10

Started by Tim Regeant in comp.arch.fpga2 days ago 1 reply

Anyone know where I can find this vintage software? I am looking for the verion 6.10 free with dongle not required. I think Synario was the...

Anyone know where I can find this vintage software? I am looking for the verion 6.10 free with dongle not required. I think Synario was the one to release the free version. Used to be at the ftp site ftp://ftp.synario.com but can't reach it now. Thanks for any help you can offer.


Low End FPGAs

Started by Rob Gaddi in comp.arch.fpga3 days ago 12 replies

So I'm looking at various platforms for general purpose, fairly low-end FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and...

So I'm looking at various platforms for general purpose, fairly low-end FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and Altera Cyclone V E all have options in the sort of * 170ish IO * Enough logic to do PLDy sort of tasks * $20ish in ~100p quantity. I've used Vivado, and Vivado's got its issues. I've used the latest Quartus Prime, and Quartus Prime's got its issue...


Looking for Xilinx HW-130/HW-120 Adapters

Started by Tim Regeant in comp.arch.fpga5 days ago 2 replies

My project needs to program a Xilinx XC7336 44PLCC. I have the software now and the HW-130 programming unit. Also have the HW-137-PC44/VQ44...

My project needs to program a Xilinx XC7336 44PLCC. I have the software now and the HW-130 programming unit. Also have the HW-137-PC44/VQ44 adapter which I assumed would work with the XC7336, but as it turns out it does not. So I need to find the adapter(s) below. If anyone can help out please let me know. HW-133-PC44 HW-133-PC68 HW-133-PC84 For reference here is webpage show...


Four_Bit_Counter in VHDL

Started by Marvin L in comp.arch.fpga6 days ago 9 replies

I am implementing four-bit-counter but I am getting value of x for Port_cou= nter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and...

I am implementing four-bit-counter but I am getting value of x for Port_cou= nter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and http://= pastebin.com/2kY3hQAN (testbench). I already finished the two flip-flop in = VHDL. I am now stuck with simulation. http://i.imgur.com/WXFQC5f.png Someone told me that the usual reason for an undefined output is failure to= initialize all ...


Four_Bit_Counter in VHDL

Started by Marvin L in comp.arch.fpga6 days ago

I am implementing four-bit-counter but I am getting value of x for Port_co= unter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and...

I am implementing four-bit-counter but I am getting value of x for Port_co= unter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and http:/= /pastebin.com/2kY3hQAN (testbench). I already finished the two flip-flop in= VHDL. I am now stuck with simulation. http://i.imgur.com/WXFQC5f.png Someone told me that the usual reason for an undefined output is failure t= o initialize al...


PADS part for ZYNQ

Started by John Larkin in comp.arch.fpga1 week ago

Hi, Does anyone have a PADS-PCB part (schematic+pcb decal) for the 484-ball ZYNQ? -- John Larkin Highland Technology,...

Hi, Does anyone have a PADS-PCB part (schematic+pcb decal) for the 484-ball ZYNQ? -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com


Multi-port memory

Started by Ilya Kalistru in comp.arch.fpga2 weeks ago 19 replies

In this article http://fpga.org/wp-content/uploads/2016/05/grvi_phalanx_fccm2016.pdf on the second page there's a description of the memory...

In this article http://fpga.org/wp-content/uploads/2016/05/grvi_phalanx_fccm2016.pdf on the second page there's a description of the memory architecture. A can't wrap around my head how did they configure 8 BRAMs to a 32KB memory with 12 independent ports. Can anybody explain this to me?


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