efinix bit stream question

Started by John Larkin in comp.arch.fpga1 day ago 10 replies

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic...

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic is compiled? Would a simple application use less? Are the streams very compressible? We have done some simple run-length coding to greatly reduce the storage requirement for other FPGAs. Configs tend to have long runs of 0's. The T20/256 claims...


Developing older Xilinx FPGA and CPLD XC3S500E

Started by Cy Drollinger in comp.arch.fpga5 days ago 2 replies

I have some old chips and in light of the shortages I continually see despi= te the 52 week lead time thrown around in the summer of 2020, I...

I have some old chips and in light of the shortages I continually see despi= te the 52 week lead time thrown around in the summer of 2020, I would like = to develop with them. Specifically, I am talking about Spartan 3E parts and= would like to know about setting up a stable toolchain with Win10 or 11. T= his could include Ubunutu 20.04 on WSL2. Does anyone have a decent recipe t= o develop ...


How to change the font size in text editor of modelsim

Started by fl in comp.arch.fpga3 weeks ago 2 replies

Hi, I am using Modelsim 6.2e with the Xilinx webpack 8.2. When I print the vhdl text from the text editor of Modelsim, the font size is very...

Hi, I am using Modelsim 6.2e with the Xilinx webpack 8.2. When I print the vhdl text from the text editor of Modelsim, the font size is very big. How to modify the font size in the printed paper? I do not find such dialogue box. Thank you very much.


Forcing Synopsys to use only DFFs

Started by Chris Johnson in comp.arch.fpga2 months ago 1 reply

I have an application that needs to assure that the FFs reloaded from the combinatorial logic at their inputs on every clock in order to flush...

I have an application that needs to assure that the FFs reloaded from the combinatorial logic at their inputs on every clock in order to flush radiation induced errors with TMR corrected values. The FPGA that I am using can implement enable FFs or D FFs. Is it possible to force Synopsys to not use only D FFs to assure that the stored values are updated on every clock? -Chris


Renesas has a 1 kLUT FPGA!

Started by gnua...@gmail.com in comp.arch.fpga2 months ago 2 replies

I guess I've heard something about this before, but it must have bounced off and not sunk in. Here's the data sheet. SLG47910...

I guess I've heard something about this before, but it must have bounced off and not sunk in. Here's the data sheet. SLG47910 - https://community.renesas.com/cfs-file/__key/communityserver-discussions-components-files/293/SL G47910_5F00_ds_5F00_2v3.pdf I guess it's not ready for production as yet. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https:/


Renesas GreenPAK Sales/FAE Support

Started by gnua...@gmail.com in comp.arch.fpga2 months ago

I've been considering a Greenpak device or two or even three, in a respin of a new design. I've identified three functions that the Greenpak...

I've been considering a Greenpak device or two or even three, in a respin of a new design. I've identified three functions that the Greenpak devices could replace on my board, but not all in the same part! LOL I'd like to discuss this design with an FAE or salesperson, but I can't seem to get any replies. The Renesas website was clearly created by pointy haired bosses in legi


32-bit Z8000 the Z80,000 and Z80320 Microprocessor

Started by Nathan Brown in comp.arch.fpga2 months ago

Looking for information about the old (Zilog) application note "Memory Management and the Z80,000 32-bit Microprocessor" (Zilog document number...

Looking for information about the old (Zilog) application note "Memory Management and the Z80,000 32-bit Microprocessor" (Zilog document number 00-2329-01).


Intel announces new FPGA families

Started by Claudio Avi Chami in comp.arch.fpga2 months ago 2 replies

https://fpgaer.tech/?p=561

https://fpgaer.tech/?p=561


Hardware based IP protection of FPGA designs

Started by gnua...@gmail.com in comp.arch.fpga2 months ago 10 replies

My customer is asking for a redesign of a very profitable board to deal with components that are EOL. Because of delivery issues from the EOL...

My customer is asking for a redesign of a very profitable board to deal with components that are EOL. Because of delivery issues from the EOL components, they are asking for the IP and manufacturing rights if I can't build them adequately. This seems a bit egregious, but I'm willing to do it if I can protect my financial interests. The ideal solution would be a device of some


Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea

Started by jg.lee in comp.arch.fpga2 months ago

Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea The [AI Accelerator Design Lab] of the...

Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea The [AI Accelerator Design Lab] of the Hallym University seek to recruit promising PhD and MSc or MSc-PhD research students. The selected students will conduct research in the [Edge Computing for Deep Learning Algorithms]. Interested applicants should contact Prof. Lee, Jeong-Gun


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