Replaceme EPROM by CPLD/FPGA

Started by Stef in comp.arch.fpga2 weeks ago 32 replies

We have a product that includes a small parallel OTP memory. These devices get very hard to get and no easy alternative is available that fits in...

We have a product that includes a small parallel OTP memory. These devices get very hard to get and no easy alternative is available that fits in the very small available space. A PLCC32 EPROM will not fit unfortunately. Since the memory array is small (256x4 bits), I was thinking this could easily fit into a CPLD or FPGA. But how to program this? The memory is used for calibration data. So...


Problem in ADV7611 with Interlace Input

Started by Swapnil Patil in comp.arch.fpga4 weeks ago 1 reply

Hello folks, We are developing demo Aplication for HDMI input and output. for this we are using PicoZed 7030 board with FMC HDMI daughter...

Hello folks, We are developing demo Aplication for HDMI input and output. for this we are using PicoZed 7030 board with FMC HDMI daughter card. the daughter card consist of Adv7611 as HDMI receiver and Adv7511 as HDMI transmitter. when progressive input is given to Adv7611 it detects progressive input and captuers Input resolution of 1920 x 1080p. register info: HDMI_INTERLACED , Addr...


FIFO timing, the right way

Started by Piotr Wyderski in comp.arch.fpga4 weeks ago 4 replies

Hi all, I am working on a block that needs to accumulate (at least) K data items and then consume them in a burst, while the next group of...

Hi all, I am working on a block that needs to accumulate (at least) K data items and then consume them in a burst, while the next group of items might be flowing in. As the items are not consumed sequentially, a very efficient approach is to have a FIFO interface on the write side and a limited lookahead random access interface one on the read side. The read side works OK. The hard par...


Up/Down Binary Counter with Dynamic Count-to Flag

Started by Anonymous in comp.arch.fpga4 weeks ago 2 replies

hello, i need to solve this problem in verilog:Up/Down Binary Counter with Dynamic Count-to Flag this is start cod: module...

hello, i need to solve this problem in verilog:Up/Down Binary Counter with Dynamic Count-to Flag this is start cod: module DW03_bictr_dcnto_inst( inst_data, inst_count_to, inst_up_dn, inst_load, inst_cen, inst_clk, inst_reset, count_inst, tercnt_inst ); parameter width = 8; input [width-1 : 0] inst_data; input [width-1 : 0] inst_count_to; input inst_up_dn; input inst_load; ...


Field update

Started by Jan in comp.arch.fpga4 weeks ago 7 replies

Dear all, What are the smartest way to make a solo FPGA project capable of field updates? I'm very new in the FPGA world so I don't much...

Dear all, What are the smartest way to make a solo FPGA project capable of field updates? I'm very new in the FPGA world so I don't much about the practical use of them. Normally when I uses microcontrollers I make them updateble via USB, serial or SD cards. What techniques are possible when I want to avoid having a uP in the project. My target is a Xilinx Spartan 3A or 3AN Reg...


FPGA board on ebay

Started by john in comp.arch.fpga1 month ago

If anyone is interested I just got round to putting up a nexys Video artix-7 board on ebay. This is a private not trade...

If anyone is interested I just got round to putting up a nexys Video artix-7 board on ebay. This is a private not trade sale. https://www.ebay.co.uk/itm/Development-Board-Nexys-Video-Artix-7-FPGA-for-M ultimedia-Applications-etc/283452707848?hash=item41ff191408:g:QzwAAOSwj1 VctIxm Feel free to contact me if you have questions but it pretty much speaks for itself. -- john ===...


BITSLIP STATE MACHINE

Started by Anonymous in comp.arch.fpga2 months ago

Hi, I am trying to design a state machine for bitslip function but simulations dont seem to be correct. I cant figure out where the bug is. here...

Hi, I am trying to design a state machine for bitslip function but simulations dont seem to be correct. I cant figure out where the bug is. here is the code and test bench. module bitsliplogic( CLOCK, RESET, DATAIN, SYNC_PATTERN, BITSLIP, BITSLIP_DONE ); parameter data_width = 10; parameter counter_width_0 = 16; parameter DELAY_0 = 10; //10 clock cycle input CLOCK; ...


High-level synthesis

Started by Benjamin Couillard in comp.arch.fpga2 months ago 28 replies

It's been about 3 years since I've done any *serious* FPGA work. I used mostly VHDL or sometimes my own Matlab scripts to create automated VHDL...

It's been about 3 years since I've done any *serious* FPGA work. I used mostly VHDL or sometimes my own Matlab scripts to create automated VHDL files. I would like to know if anyone has used High-level synthesis recetnly for *real* work and if so, would they recommend that people learn it?


TCS34725 Basys3 VHDL

Started by Anonymous in comp.arch.fpga2 months ago 1 reply

Hi I am trying to use TCS34725 to identify Green and Red Colors, it has I2C interface and i could not find any I2C interface about this and i am...

Hi I am trying to use TCS34725 to identify Green and Red Colors, it has I2C interface and i could not find any I2C interface about this and i am not capable to write a protocol code what should I do I am stucked. I just need when it sees green it turns one led and when it sees red it turns another led.


Hello

Started by Anonymous in comp.arch.fpga2 months ago 3 replies

Hi all, New to this list. I'm Gerard, Ham Radio operator F6EEQ. I have a Papilio Pro(Xilinx Spartan 6 LX)development platform since 5 or 6...

Hi all, New to this list. I'm Gerard, Ham Radio operator F6EEQ. I have a Papilio Pro(Xilinx Spartan 6 LX)development platform since 5 or 6 years. But did not di much with it. Read an article in G-QRP club magazine "SPRAT" about DDS with FPGA and this renewed my interest. Hope to find much help and info here. See you soon. Gerard


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