No more gate-level simulation. for Cyclone V !!!

Started by Luis Cupido in comp.arch.fpga10 hours ago 4 replies

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a...

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a Cyclone V I found that I can't do timing gate-level timing simulation, quartus does not generate the SDF file, the *.sdo file. Altera/Intel says this on the documentation regarding simulation: "Gate-level timing simulation is supported only for the...


Fight the coronavirus 100% and save LOTS of CASH -- Combattez le coronavirus 100% et économisez BEAUCOUP d'ARGENT

Started by Anonymous in comp.arch.fpga6 days ago

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Use example of Intel University program in Intel Quartus - problem with Board support package?

Started by Bliad Bors in comp.arch.fpga1 week ago 4 replies

I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box...

I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box on the HDMI output and writes a littel String with white letters on top of it. I want to use it in Intel Quartus environment , do some test-outputs on my screen and finally add some more Hardware to the Avalon system. Unfortunately it doe


PipelineC - C-like almost hardware description language - AWS F1 Example

Started by Julian Kemmerer in comp.arch.fpga2 weeks ago 2 replies

Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost hardware description...

Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost hardware description language - A compiler that produces VHDL for specific devices/operating frequencies I am looking for: - anyone who wants to help me develop (Python, VHDL, C) - suggestions on how to make PipelineC more useful/new features - project ideas (heyo open...


Using EDA tools at home

Started by Anonymous in comp.arch.fpga2 weeks ago

Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to speak to your EDA...

Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to speak to your EDA vendor= , I am sure all have solutions for you and some even give you a free tempor= ary license (if you are an existing customer). 2) If you have a node locked license, simply take the dongle home. 3) If you have a MAC based license then try to spoof the MA...


Is FPGA code called firmware?

Started by Marko in comp.arch.fpga1 month ago 80 replies

Traditionally, firmware was defined as software that resided in ROM. So, my question is, what do you call FPGA code? Is "firmware" appropriate?

Traditionally, firmware was defined as software that resided in ROM. So, my question is, what do you call FPGA code? Is "firmware" appropriate?


Code block in icestudio

Started by Josef Moellers in comp.arch.fpga1 month ago 17 replies

Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using an ATMega...

Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using an ATMega ucontroller. To sort out the A0,nCS,nRD,nWR,nDACK, I have inserted a code block which should generate the following internal signals: SEL: switch a "Mux 2:1" between the outputs of the STATUS and the DATA IN registers OE: enable a TRI-STATE output to the pr...


How to generate bits info for a record structure?

Started by Weng Tianxiang in comp.arch.fpga2 months ago 9 replies

Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downto 0); end...

Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downto 0); end record; I want to get its bit number and don't want to manually calculate the bit number. How can I do it? Thank you. Weng


how to suppress assertion warnings in gtkwave?

Started by the clever Bit in comp.arch.fpga2 months ago 3 replies

hello, is there any way to suppress assertion warnings from std.numeric in gtkwave simulator? thank you

hello, is there any way to suppress assertion warnings from std.numeric in gtkwave simulator? thank you


Apple eBook on Educational CPU design using FPGA

Started by Othman Ahmad in comp.arch.fpga3 months ago

https://books.apple.com/us/book/implementing-a-cpu-using-fpga/id802454238

https://books.apple.com/us/book/implementing-a-cpu-using-fpga/id802454238


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