Looking for MMI M2018 LCA data sheet

Started by Zach Metzinger in comp.arch.fpga2 weeks ago 15 replies

Hello, I'm a collector and tinkerer of old, archaic devices, and I recently came across a MMI M2018-20CP (date code 81xx) in a PGA...

Hello, I'm a collector and tinkerer of old, archaic devices, and I recently came across a MMI M2018-20CP (date code 81xx) in a PGA package. I've found the M2064 data sheet, but I can't seem to track down the M2018 data sheet from MMI/AMD. I'm also looking for the MMI XACT tools of the same era that would support generating the data pattern (what we might call a configuration bitstr...


fixed point modeling tools

Started by Anonymous in comp.arch.fpga4 weeks ago 4 replies

Hello,=20 For those of you who do DSP modeling in Python, I've recently released a pa= ckage that supports fixed point arithmetic. The...

Hello,=20 For those of you who do DSP modeling in Python, I've recently released a pa= ckage that supports fixed point arithmetic. The existing open source tools = are lackluster and MATLAB doesn't nicely fit into our simulation/testing wo= rkflow. Just trying to get the word out for a higher adoption rate! Documentation is here: https://fixedpoint.readthedocs.io Gihub repo is here: ...


Passing digitized data to design

Started by Mohammed Billoo in comp.arch.fpga4 weeks ago 5 replies

Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification?...

Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification? I'm getting into FPGA development and have created a simple filter. I wanted to test it out on audio data that I can generate and see that the filter actually works, but I haven't found a way to actually "pass" data to a design. Thanks Moh


coronavirus COVID-19

Started by Anonymous in comp.arch.fpga1 month ago

coronavirus COVID-19 http://www.grex.org/~henced/coronavirus.html

coronavirus COVID-19 http://www.grex.org/~henced/coronavirus.html


CFP IEEE International Conference on Computer Design (ICCD) 2020

Started by Pillement in comp.arch.fpga2 months ago

------------------------------------------------------------------ Call for...

------------------------------------------------------------------ Call for Papers ------------------------------------------------------------------ 2020 IEEE International Conference on Computer Design (ICCD) Oct 18-21, 2020 Hartford, Connecticut USA -----------------------------------------------------------...


CPU Softcore Compendium

Started by Rick C in comp.arch.fpga2 months ago 1 reply

Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per...

Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per clock and a performance metric incorporating all three. I don't recall the author's name, but it was amazingly complete. Anyone remember that? Still got the link? -- Rick C. - Get 1,000 miles of free Supercharging - T


No more gate-level simulation. for Cyclone V !!!

Started by Luis Cupido in comp.arch.fpga2 months ago 8 replies

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a...

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a Cyclone V I found that I can't do timing gate-level timing simulation, quartus does not generate the SDF file, the *.sdo file. Altera/Intel says this on the documentation regarding simulation: "Gate-level timing simulation is supported only for the...


Terminated

Started by Jeff Hickling in comp.arch.fpga2 months ago 2 replies

2017 Dennis terminated from the Public Library. Failure to perform guard duties. Last week, the week of June 19th, Dennis was summarily...

2017 Dennis terminated from the Public Library. Failure to perform guard duties. Last week, the week of June 19th, Dennis was summarily discharged from his position of library security guard by new interim librarian, apparently a young woman not to be ?truffled? with. The new librarian cited the primary reason for Officer D?s summary dismissal as a ?failure to act in accorda


Fight the coronavirus 100% and save LOTS of CASH -- Combattez le coronavirus 100% et économisez BEAUCOUP d'ARGENT

Started by Anonymous in comp.arch.fpga2 months ago

Protect yourself and your loved ones ! KILL the coronavirus right now ! And save LOTS OF CASH New tested, scientificly proven and amazing...

Protect yourself and your loved ones ! KILL the coronavirus right now ! And save LOTS OF CASH New tested, scientificly proven and amazing antivirus against coronavirus using Chloroquine and Colchicine at very low price (33% discount) Satisfaction garanteed or your money back ! http://als0p.atwebpages.com/coronavirus/coronavirus-en.php Prot?gez-vous et vos proches! TUEZ le coronavirus...


Use example of Intel University program in Intel Quartus - problem with Board support package?

Started by Bliad Bors in comp.arch.fpga2 months ago 4 replies

I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box...

I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box on the HDMI output and writes a littel String with white letters on top of it. I want to use it in Intel Quartus environment , do some test-outputs on my screen and finally add some more Hardware to the Avalon system. Unfortunately it doe


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