Is FPGA code called firmware?

Started by Marko in comp.arch.fpga2 days ago 81 replies

Traditionally, firmware was defined as software that resided in ROM. So, my question is, what do you call FPGA code? Is "firmware" appropriate?

Traditionally, firmware was defined as software that resided in ROM. So, my question is, what do you call FPGA code? Is "firmware" appropriate?


Elastic buffer implementation

Started by promach in comp.arch.fpga3 days ago

For this article : Implementing Latency-Insensitive Dataflow Blocks at http://arcade.cs.columbia.edu/lid-memocode15.pdf#page=2 1) How is "Hold"...

For this article : Implementing Latency-Insensitive Dataflow Blocks at http://arcade.cs.columbia.edu/lid-memocode15.pdf#page=2 1) How is "Hold" action different from "Buffer" action ? 2) Why is the '1' pin of the second multiplexer inside the input buffer block fed a symbol of ⊥ ?


Some preliminary help for an FPGA selection

Started by Dimiter_Popoff in comp.arch.fpga5 days ago 4 replies

It will be the first FPGA for me. What I want to do is not complex, I have done similar controllers (more complex really)numerous times using...

It will be the first FPGA for me. What I want to do is not complex, I have done similar controllers (more complex really)numerous times using logic parts, PLD, CPLD-s etc. I need to put together a display controller, to just do framebuffer memory -> display interface. Framebuffer memory will be some sort of DDRAM (DDR-which depending on the FPGA type), I'll be happy with a 1920x1080 framebuf


VLSI SUBSCRIBE

Started by Chip training design in comp.arch.fpga6 days ago

Hi All, ...

Hi All, https://www.youtube.com/watch?v=lT1dj_gmHuM&list=PLesx0GVGgym1bHV1gPIl89wnY0KFflLHj&index=1 https://www.youtube.com/watch?v=YSyz971kuU0&list=PLesx0GVGgym1bHV1gPIl89wnY0KFflLHj&index=10 https://www.youtube.com/watch?v=am6jPpJazx4&list=PLesx0GVGgym1bHV1gPIl89wnY0KFflLHj&index=11 https://www.youtube.com/watch?v=4leMX8s3A0E&list=PLesx0GVGgym1bHV1gPIl89wnY0KFflLHj&index=5 http...


Entity-bound SDC file in Quartus Lite Edition?

Started by Anonymous in comp.arch.fpga2 weeks ago 1 reply

Hi, I need to port my design from Xilinx FPGA based board to a Altera/Intel FPGA based one. The design must be available for students, who need...

Hi, I need to port my design from Xilinx FPGA based board to a Altera/Intel FPGA based one. The design must be available for students, who need to use the Quartus Lite Edition. One of essential things in the design is the usage of "scoped timing constraints" (obtained in Vivado with SCOPED_TO_REF attribute). I have found that a similar option is available in Quartus as "entity-bound SDC file...


Open source Verilog BCH encoder/decoder

Started by Russell Dill in comp.arch.fpga1 month ago 10 replies

As part of my research, I needed a BCH encoder/decoder engine. Sadly, such = a thing has no existed under a permissive license. Even more...

As part of my research, I needed a BCH encoder/decoder engine. Sadly, such = a thing has no existed under a permissive license. Even more depressing is = that many students seem to submit Verilog or VHDL engines as a project (or = even research), but never release anything that is usable. Anyway, I'm releasing a BSD licensed Verilog BCH encoder/decoder. It offers= : * Parallel input/outp...


Need help finding Synario Futurenet 6.10

Started by Tim Regeant in comp.arch.fpga1 month ago 2 replies

Anyone know where I can find this vintage software? I am looking for the verion 6.10 free with dongle not required. I think Synario was the...

Anyone know where I can find this vintage software? I am looking for the verion 6.10 free with dongle not required. I think Synario was the one to release the free version. Used to be at the ftp site ftp://ftp.synario.com but can't reach it now. Thanks for any help you can offer.


ICCD 2020: Call for Special Sessions and Tutorial Proposals

Started by Pillement in comp.arch.fpga1 month ago

=========================================================== ICCD 2020: Call for Special Sessions and Tutorial...

=========================================================== ICCD 2020: Call for Special Sessions and Tutorial Proposals ==================================================


CPU Softcore Compendium

Started by Rick C in comp.arch.fpga1 month ago 4 replies

Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per...

Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per clock and a performance metric incorporating all three. I don't recall the author's name, but it was amazingly complete. Anyone remember that? Still got the link? -- Rick C. - Get 1,000 miles of free Supercharging - T


Driving crystal with cheap FPGA ( MAchXO2) directly ?

Started by Brane 2 in comp.arch.fpga1 month ago 29 replies

I tireid using ust a pin pair and inverting function. But with LVCMOS333 on Breakout Board ( 3,3V for I/O), MachXO implements hysteresis on...

I tireid using ust a pin pair and inverting function. But with LVCMOS333 on Breakout Board ( 3,3V for I/O), MachXO implements hysteresis on input and this seems to hamper the oscillations. I can't start the crystal reliably. If oscillation starts, it runs fine. I used siimple 24MHz quartz with 1M across and 22pF toward GND on each side. Can't find anythong on the matter on Lattice... ...


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