Communication between HDL simulation and user software via ZMQ

Started by Anonymous in comp.arch.fpga41 minutes ago

I develop systems were the FPGA-based hardware will use message-based communication (via Ethernet, USB or another communication channel) with...

I develop systems were the FPGA-based hardware will use message-based communication (via Ethernet, USB or another communication channel) with remote software. Those systems require thorough testing in simulations. Therefore I needed to create a mechanism for communication between the simulation and software using the remote message-passing library like ZeroMQ. The first version was


CPLD 1.8V to 3.3V bidirectional SDA

Started by nobody in comp.arch.fpga3 days ago 10 replies

I have a small design flaw with a new sensor, ICM20948, into a PI device. I need to make the SDA bidirectional and level shift SCL, int, and...

I have a small design flaw with a new sensor, ICM20948, into a PI device. I need to make the SDA bidirectional and level shift SCL, int, and fsync. Voltage level on the sensor board is 1.8V the PI is 3.3V. I have CPLD hardware that I would like to use to make the bidirectional level shifted SDA as well as level shift the other three. The VHDL behavior is as simple as: begin en


FPGA selection recommendation

Started by Piotr Wyderski in comp.arch.fpga5 days ago 25 replies

I need an FPGA chip with about 100 GPIO pins and capable of hosting a CPU with an existing Linux port, mainly to run a web server. I would like...

I need an FPGA chip with about 100 GPIO pins and capable of hosting a CPU with an existing Linux port, mainly to run a web server. I would like to connect it to a 16-bit DRAM, so there should exist a memory controller with this feature, either a hard macro or a soft IP core. There should also be a fast ethernet MAC. Nothing fancy, but: 1. This is for a small non-profit project, so the IP...


CAN Sniffer on Altera DE2-115 Board

Started by Ryo Kato in comp.arch.fpga2 weeks ago

Hi there, I am trying to implement a CAN sniffer on an Altera DE2-115 evaluation board with the Terrasic AD/DA data conversion card (High Speed...

Hi there, I am trying to implement a CAN sniffer on an Altera DE2-115 evaluation board with the Terrasic AD/DA data conversion card (High Speed Mezzanine Card (HSMC) via SMA. I am using two A/D channels for CAN_H and CAN_L bus signals. Before testing it with real CAN signals I want to make sure that the connection is right in terms of voltage swing, differential termination and peak


verilog reg usage

Started by promach in comp.arch.fpga3 weeks ago 1 reply

Does

Does


Sharing VHDL Verification IP

Started by Espen Tallaksen in comp.arch.fpga3 weeks ago

Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community has previously been difficult because there was no standardised way of...

Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community has previously been difficult because there was no standardised way of interfacing to and controlling these VVCs. A solution on this challenge could easily reduce the project verification time by 20 to 80%, and at the same time improve the FPGA quality. The open source UVVM has over the last two years standard


engineered data path versus inferred data path

Started by Anonymous in comp.arch.fpga4 weeks ago 5 replies

Seem to get better results when using inferred data paths? E.g. letting the synthesis tools insert the multiplexers where they see fit gives...

Seem to get better results when using inferred data paths? E.g. letting the synthesis tools insert the multiplexers where they see fit gives better Fmax than laying out the datapath in complete detail. Also don't need to remember and code all the control signals for the muxes. Still code intermediate adders and such to keep the number of inferred carry chains down. Comments? Jim Brakefi...


Xilinx Custom IP accessing 16-bit bram

Started by Norman Lo in comp.arch.fpga4 weeks ago

Hello, I have used Xilinx core generator to synthesize a bram with width of 16 bit and depth of 80k, resulting a 17-bit address. Let's call...

Hello, I have used Xilinx core generator to synthesize a bram with width of 16 bit and depth of 80k, resulting a 17-bit address. Let's call them bram_data, and bram_addr. I am connecting the bram to PLB bus which has 32-bit address (Bus2IP_Addr) and 32-bit data (Bus2IP_Data). I am not sure how to connect those two together since I don't understand that if the address is not at the...


the FPGA one-shot

Started by John Larkin in comp.arch.fpga2 months ago 13 replies

I finally got a test case for my FPGA async one-shot idea, hacked into a build for something else. I got 17 different one-shots, with various...

I finally got a test case for my FPGA async one-shot idea, hacked into a build for something else. I got 17 different one-shots, with various pin locations and speed/drive strength settings. https://www.dropbox.com/s/4hxena27mpbpg54/FPGA_OS_1.JPG?raw=1 Most of the outputs look like this, with remarkably consistent timing, edges within a few hundred ps. This is typical: https://ww...


Altera Cyclone V SoC availability...

Started by Brane2 in comp.arch.fpga2 months ago 1 reply

I can't find it anywhere. No one carries Cyclone V SX/T, only plain E or Gx...

I can't find it anywhere. No one carries Cyclone V SX/T, only plain E or Gx...


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