consulting job / Xilinx Artix MGT POR

Started by Tobias Kahre in comp.arch.fpga2 days ago

Hi there, I am looking for an expert on how to by-hand-configure MGTs individually of an single quad. I have an Artix 35T, the first MGT has...

Hi there, I am looking for an expert on how to by-hand-configure MGTs individually of an single quad. I have an Artix 35T, the first MGT has to do aurora, the second and third one has to do JESD204b. I am offering a consulting fee for teaching me personally and/or working design of POR up to exchange of comma characters. Cheers, Tobias


VHDL or Verilog?

Started by Rick C. Hodgin in comp.arch.fpga5 days ago 20 replies

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use...

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use VHDL, and others who tell me Verilog. Most everybody tells me that if I use VHDL there's less chance for error, but that it does take more effort to learn. Any thoughts? Thank you, Rick C. Hodgin


Create FPGA to replace 1974 MOSTEK MK5017

Started by Anonymous in comp.arch.fpga1 week ago 3 replies

Hi Everyone, Perhaps you may have a skill to create FPGA and create a clone for 1974 MOSTEK MK5017, famous clock chip by Heathkit. They used...

Hi Everyone, Perhaps you may have a skill to create FPGA and create a clone for 1974 MOSTEK MK5017, famous clock chip by Heathkit. They used this chip on model GC-1005 and run with Panaplex display tubes by Sperry Rand. Unfortunately, MOSTEK went out of business (thanks to US EPA that destroyed wonderful company by enormous fines instead of help to clean). Nowdays, it is impossib


Whups. Lattice Diamond says my package does not exist.

Started by Anonymous in comp.arch.fpga2 weeks ago 5 replies

Hi all. I'm stopped. Lattice Diamond does not offer a configuration for designing with my part in the 48-VFQFN package. The LCMXO2-640HC-6SG48I...

Hi all. I'm stopped. Lattice Diamond does not offer a configuration for designing with my part in the 48-VFQFN package. The LCMXO2-640HC-6SG48I is not available in the drop-down configuration menu. They say the closest they can get is the TQFP-100 or CSBGA-132 packages. My PCB and FPGA arrived days ago but I need a way to do development! Is there a way to configure Lattice Diamond


Article about using Non-Project Mode

Started by Ilya Kalistru in comp.arch.fpga2 weeks ago 7 replies

Hi! During the discussion about "Test Driven Design?" I promised to write a paper about Non-Project Mode and how it helps with testing. The...

Hi! During the discussion about "Test Driven Design?" I promised to write a paper about Non-Project Mode and how it helps with testing. The problem is that I have never written any article. Moreover, English is not my native language. I kindly ask you to review the article and help me to improve it. It is in Google docs and leaving comments right in the document is allowed. You also can comment...


ZAP : An open source ARM processor (feedback)

Started by Anonymous in comp.arch.fpga4 weeks ago 19 replies

Hi, I am the author of the Gihub project ZAP ( https://github.com/krevanth/ZAP ). It is a 10-stage pipelined ARMv4T compatible soft processor...

Hi, I am the author of the Gihub project ZAP ( https://github.com/krevanth/ZAP ). It is a 10-stage pipelined ARMv4T compatible soft processor core with cache and memory management support. I developed it during my final semester in university. Would like your feedback/criticism of the project. Thanks, K Revanth


baud_generator (16x baud) used in UART transmitter logic

Started by _Xilinx in comp.arch.fpga4 weeks ago 3 replies

For http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the output of baud_generator (16x baud) used in transmitter logic ? I only...

For http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the output of baud_generator (16x baud) used in transmitter logic ? I only see there is a transmitter timing control block in the functional block diagram, but I am not sure how it works exactly. Anyone ?


Test Driven Design?

Started by Tim Wescott in comp.arch.fpga4 weeks ago 44 replies

Anyone doing any test driven design for FPGA work? I've gone over to doing it almost universally for C++ development, because It Just Works...

Anyone doing any test driven design for FPGA work? I've gone over to doing it almost universally for C++ development, because It Just Works -- you lengthen the time to integration a bit, but vastly shorten the actual integration time. I did a web search and didn't find it mentioned -- the traditional "make a test bench" is part way there, but as presented in my textbook* doesn't impo...


May.25.2017 -- A plea for help

Started by Rick C. Hodgin in comp.arch.fpga1 month ago 18 replies

This world is run by evil madmen being guided by an insane evil spirit named Satan. The purpose of all of Satan's actions are to do...

This world is run by evil madmen being guided by an insane evil spirit named Satan. The purpose of all of Satan's actions are to do the opposite of that which God established, and to teach contrary things to that which God established. I would like to request help in changing that. The Lord Jesus Christ came to this Earth to restore that which was lost because of sin. He did that at th...


fpga zigbee interface

Started by Anonymous in comp.arch.fpga1 month ago 2 replies

i have spartan6 atlys(LX45) board, can anyone suggest me how to interface zigbee to this board to communicate with pc.thnx

i have spartan6 atlys(LX45) board, can anyone suggest me how to interface zigbee to this board to communicate with pc.thnx


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