• SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling | | | |
• Verification Methodology Manual for SystemVerilog | | | |
• Writing Testbenches using SystemVerilog | | | |
• Step-by-step Functional Verification with SystemVerilog and OVM | | | |
• FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version | | | |

for beginners only
Review written by: whiteplains From
This book is written for entry level verification engineers. If you are an experienced professional with experience in Vera or e, then you are better off viewing testbenches on the internet (for free). That said, by comparison, this book may be better than much of the overpriced engineering crap in print today.

Good reference for higher level concepts
Review written by: Nomuri From Austin, TX
I have only read a few chapters in this book, and it is well written, easy to understand and gives a good examples. If you are new to implementing OOP in HDL or are looking for methodologies and good practices to start writing SV test benches than this is a good read for you. I would not recommend however to the absolute new user of SV, this book tends not to spend much time on the "little things". It breezes by the data types section and hardly mentions anything of properties, sequences, and assertions to name a few, which I have found are pretty useful in SV test benches. I recommend this book for a user looking for methodology, OOP, and practical test bench reference, and not for someone looking for a "complete" reference of SV.

Excellent book for systemVerilog newbie
Review written by: S. Li From
This is an excellent systemVerilog introduction book, if you are experienced verilog user want to learn systemVerilog, this book is the right one for you. Highly recommend to anyone who want to utilize systemVerilog features to enhance their current verification environment.

Excellent Starter Book For Newbies
Review written by: E. Hamel From Ottawa, ON, Canada
I purchased this book since I had to implement a new verification environment from scratch. I read the entire book, and I was off building a verification environment with SV.

There are few details which are not discussed in the book, for instance how to import classes into other classes(from a package), and how you should compile the entire project (again from a package).

Overall, if you don't know SV, and OOP, this is an excellent book to start with.

Excellent book except for ...
Review written by: Timothy H. Pylant From Austin, TX United States
a few non-compliant code examples that do not follow the IEEE LRM. With that said, overall the book contains a number of good examples and covers the SV language. It doesn't spend much time discussing methodology (which can be good or bad depending on what you're looking for).

In summary, decent reading and a good language reference. Definitely a lot better than the VMM book.