• SystemVerilog for Verification: A Guide to Learning the Testbench Language Features | | | |
• Open Verification Methodology Cookbook | | | |
• SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling | | | |
• The Art of Verification with SystemVerilog Assertions | | | |
• A Practical Guide for SystemVerilog Assertions | | | |

Excellent OVM Information; But examples need editing to compile and simulate
Review written by: Debra Klopfenstein From Philadelphia, PA
I needed to become deeply familiar with OVM. This book is an excellent source of information that I have not found anywhere else. Iman is thorough and detailed. THe Step-by-Step layout works great.

But just note that the OVM examples in the 2nd half of the book are based on OVM-1.01. The OVM-1.01 examples in the book do not compile without some editing if you are using the latest release of OVM (I am currently using ovm-2.0.1). I emailed the author about this. [...]

The good news is editing the examples is not that bad if you grep through the ovm-2.0.1/src directory for information. The examples are well-put together and highlight Iman's concepts well. And once the edits are made, the examples run great.

Excelent Intro for both OVM and SystemVerilog!
Review written by: Jeffery S. Vance From Pittsburgh, PA United States
I'm a computer engineering graduate student and wanted to learn SystemVerilog and OVM to help pursue a career as a verification engineer. I found this book to be an incredible wealth of information while also being fun to read.

This book was perfect for my background. I had only done design with VHDL and was exposed to some basic verification methods using testbenches written in "e" for Specman. I wanted to learn OVM, but had no exposure to SystemVerilog or even Verilog. This book was perfect since it devotes an entire section to SystemVerilog before focusing on OVM. Although it would certainly help to know the basics of Verilog before reading this book, I don't think it is required. I had no issues picking up the syntax and knowledge to quickly start writing SystemVerilog testbenches.

Part 1 is entirely dedicated to Verification Methodologies. Many topics in this section I had previous exposure to from other books or classes. However these topics are presented with more depth and clearer examples from my previous readings and I ended up greatly expanding my understanding. This is also a great introduction to verification for anyone new to these topics.

The most useful part of this book for me are the examples. The examples are written so that they are simple enough to understand new concepts, while also demonstrating how they could be expanded to do much more complex things. As a learning experience, I found it very easy to just copy the examples and modify the code to suit the design I wanted to verify. And the examples are described so you understand exactly what every line is doing.

I also really liked the chapters on Coverage Modeling and Measurement. This clarified a lot of confusion I had about how coverage modeling is practically applied to designs. The book explains much more than just how to write SystemVerilog code for coverage monitoring. It also explains methodologies of defining coverage metrics for a verification plan, using an example design spec as an example.


In summary: Coming from someone new to the world of verification, this is an excellent introduction to Verification Methodologies, SystemVerilog, and OVM. This one book covers all three of these topics equally well. Before finding this book, I was worried I'd have to purchase 3 books dedicated to each of these topics.

well organized and very concise
Review written by: M. HSU From Silicon Valley, CA
(disclaimer - we're being offered an extra copy for a review)

Even though though the extra copy is an incentive to write this review, the offer did not in any way suggest using any bias. I've been a verification engineer for the better part of 20 years and I hope you will consider this review impartial.

So far I have carefully read up through part 3 (chapters 1-9, pages 1-235 of 520)

Overall, this is a very concise and well thought out reference for anyone wishing to become proficient at writing SystemVerilog/OVM testbenches. While prior knowledge of other verification methodologies and languages are not required to understand the concepts and structure of testbenches using OVM laid out in this book, it is required if you actually want to create verification testbenches and tests using OVM. This book does not provide that background.

Part 1 - Chapters 1, 2 & 3

These chapters are dedicated to outlining verification and verification methodology principles. It is a must read if you've never been exposed to a well thought out verification methodology. Of the hundreds of verification candidates I've interviewed, only around 10% appear to know this. If all you get out of this are the principles here, this book will be worth your money.

Part 2 - Chapters 4 & 5

These chapters review some new things that are in SystemVerilog. Although it suggests that they are "All About SystemVerilog" they are not. This is good as I expected and wanted this book to be more about verification and OVM than SystemVerilog. Don't look to this book as a SystemVerilog reference. It is interesting that there is a separate chapter for "SystemVerilog as a Verification Language". While the brief list of differences are true, both designers and verification would benefit from the explanations.

Part 3 - Chapters 6, 7, 8 & 9

This is the meat of the book (so far). Individual pieces of the OVM method are illustrated with examples and text. The author does an admirable job of concisely providing and describing code that, while dry, is fairly clear. It tends to be somewhat minimalistic showing only form and structure. I would prefer a little more reasoning behind why certain things were done in certain ways - not just for verification but why was the methodology constructed the way it was.

That's all I've gotten to and will refrain from comment on what I have not read yet. Hopefully I will be able to add more commentary when I am finished with the book.

In summary, this is an excellent choice (and one of the few!) for verification engineers who need to come up to speed with OVM. On the plus side, the material encourages what I would consider the best verification practices available today. On the minus side, the text and examples are sometimes a little to brief and when I try to use it as a reference, it is sometimes hard to find what I need quickly.

SystemVerilog and OVM are the future
Review written by: Von L. Wolff From I live in Chippewa Falls, WI

I believe that even a college graduate could benefit from this book, as it shapes one's thinking toward a future where design verification is more
important than design. As a design and verification engineer, I realize
that books like this one are essential for my continued education. I have used almost every verification tool you can think of. I have learned these tools with and without help. Trust me, this book is the kind of help you need.

A great deal of the time, thought and effort must have been put into the teaching of SystemVerilog in this book, because I was able to pick up the concepts with ease. I saw original examples and great detailed explanations of the features of SystemVerilog. This book also provided me with an in depth look at what OVM is and how it helps to simplify the complex task of verifying ASICs. Without OVM we are limited to verifying the simple and small FPGAs in this world. Without learning SystemVerilog we would relegated to doing VHDL for the rest of our short careers. This book teaches both OVM and System Verilog. Read this book and you will understand why you need these tools and how you can benefit from this new technology.

A full class-based verification system.
Review written by: Jorge V. Blasco Claret From Valencia, SPAIN
Reviewer: José Calero Title: CTO Company: DS2

Book: Step-by-Step Verification Using SystemVerilog and OVM

Finally, a nice to read and straight-forward book that clarifies the basic and advanced concepts behind modern SoC verification and behind the OVM methodology.

Before reading this book, I had the feeling that OVM, although very
powerful, had a painful and long learning curve. This is not anymore the case. The book drives you from the verification basics to the advanced topics, and it does that for both the newcomer and the verification expert willing to know about OVM. In particular, for readers with a previous experience in SoC design, the author introduces the "module-based" approach to verification environments which helps to change-the-mind towards a full class-based verification system.

The book is full with a selected set of example the author uses to describe the topics in a constructive manner (piece of code presented first are used later within examples that describe more complex concepts or complete scenarios). Part 5 of the book, "Environment Implementation and Scenario Generation", wraps-up all the concepts with a complete example.