An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

An Overview of Low Power Techniques for FPGAs

Introduction

Field Programmable Gate Arrays (FPGAs), due to their re-configurability and flexible hardware architecture allow large-scale parallel processing and pipelining of dataflow. These processing capabilities of FPGAs make them a perfect choice for implementation of adaptive and real-.time systems, where the system’s fast response time is critical for smooth functioning of the system. Such adaptive systems have the capability to respond to the environmental conditions and changing demands by modifying their processing at real time. FPGAs can be configured by the user in order to implement digital logic functions of varying complexities. Latest FPGAs provide plenty of processing resources, enormous on-chip RAM, and high I/O capability and can be operated at very high clock speeds. FPGAs are now used to implement entire systems on a chip (SoC’s) rather than the small logic sub-circuits that have traditionally been targeted to FPGAs [7].The main advantages of FPGAs include ability to be programmed and reconfigured in the field, short time-to-market and non-recurring engineering costs.

The global market of FPGAs is growing rapidly and, according to TechNavio’s forecast, it is expected to reach $5.6 billion in 2014. The key factor behind this rapid growth is the flexibility offered by FPGAs in developing customized designs, and the efforts made by the FPGA vendors to tackle growing design complexities [2].

The major drawback of FPGAs is that their power efficiency and speed are considerably lower than that of application-specific integrated circuits (ASICs) due to the additional circuitry required to make them reconfigurable.The flexible nature of an FPGA comes at a significant cost in area,delay and power consumption: an FPGA requires approximately 20 to 35 times more area than a standard cell ASIC,has a speed performance roughly 3 to 4 times slower than an ASIC and consumes roughly 10 times as much dynamic power.These diadvatnages arise largly from an FPGA’s programmable routing fabric which trades area,speed and power in return for instant fabrication  [46].

FPGA vendors report that power consumption is one of the primary concerns of their customers. Compared to ASICs and other custom chips, FPGAs contain long routing tracks with significant parasitic capacitance; during high speed operations, the switching activity on these long routing tracks causes significant power dissipation[3].

Traditionally, FPGA power consumption has been less of a concern compared to their speed and area efficiency,but high density of transistors on the same chip has made power consumption one of the major challenges of deep submicron IC design  [45].In the recent years, due to process scaling resulting in increased power dissipation per unit area and increasing demand for low-power applications driven by proliferation of hand-held devices and soaring energy prices, much of the focus of FPGA research has shifted to improving energy efficiency and lowering power dissipation [1]. For portable battery-operated devices like cell phone, iPod, Laptop and Tablet PC etc., reducing power consumption improves battery life. While for non-portable electronic devices, like desktop computer, TV and home entertainment system etc., reducing overall power consumption requirements, lowers operating, packaging and cooling system costs.

There are several techniques to improve the energy efficiency of FPGAs, which can be broadly divided into five categories [1]: process, circuit, architecture, system and computer aided design (CAD).In Process techniques low power processing technologies, offered by semiconductor manufacturers, are utilized to reduce the power consumption. Circuit techniques involve transistor-level implementation of logic and routing resources. Architecture techniques refer to efficiently and precisely managing functionality of the logic, I/O, and memory resources and the connectivity between these resources. System techniques refer to high-level low-power techniques such as dynamic voltage control, turning resources off when they are not being used, and run-time reconfiguration. Finally, CAD refers to enhancements made to the mapping tools which are used to configure the FPGA.

 Sources of Power Dissipation in FPGA

To better understand why the power efficiency of FPGAs is low, it is necessary to understand the architecture of FPGAs. FPGAs dissipate more static power than ASICs [1]. FPGAs,as illustrated in Figure 1,consist of an array of logic blocks of potentially different types,including general logic,memory and multiplier blocks,surrounded by a programmable routing fabric that allows blocks to be programmably interconnected.The array is surrounded by progammable input/output blocks,labeled I/O in the Figure 1,that connect the chip to outside world [46]. In an FPGA based digital system design, these logic blocks implement the logic part of digital circuits. The programmable routing fabric and configurable logic blocks in FPGAs are controlled by a large amount of configuration memory and this configuration memory dissipates static power. The look-up tables (LUTs) in FPGAs, that are used to implement programmable logic blocks, contain considerably more transistors than the corresponding logic gates in an ASIC. A large number of multiplexers are used in FPGAs to make the programmable routing fabric flexible enough to make FPGAs re-configurable and architecturally flexible. These routing resources in FPGAs require considerably much more transistors than in ASICs.

FPGAs are power-hungry for many reasons. First, the lookup tables that are used for implementing digital logic have not been optimized for a specific application. Second, the prevalence of programmable switches in the interconnect leads to high-interconnect capacitances, and hence, high switching energy [10].The power consumed in an FPGA core comprises both static and dynamic components. Static power constitutes about 10% of the total power consumed in an FPGA, while dynamic power constitutes about 90% of the total power consumed in an FPGA [6].

FPGAs, due to having significantly more parasitic capacitance than in ASICs, also dissipate more dynamic power than ASICs. Parasitic capacitance in both FPGA and ASIC is caused by the metal wire used to implement the connection as well as the driver and driven transistors [1]. Charging and discharging this parasitic capacitance consumes dynamic power. Unlike ASICs, a connection in an FPGA contains a large number of programmable switches that cause the parasitic capacitance in FPGAs to be significantly larger than in ASICs.

Figure 1 Internal Architecture of a Generic FPGA [46]

A breakdown of core power consumption in a commercial 90-nm FPGA is shown in Figure 2 [4].According to this Figure, the greatest amount of power dissipated in routing resources. While logic and clock network resources also dissipate a significant amount of power.

Figure 2 Breakdown of Core Power Consumption in Xilinx Spartan-3 Devices [4]

According to another research [5], FPGAs with embedded memories have been found to account for 14% of core dynamic power.

Undesirable and spurious signals at the output of combinational components, called glitches that result in undesirable switching activity and dynamic power dissipation, caused by the input signals arriving at different times, because of unequal input propagation delays, are also a major source of power dissipation in FPGAs [8].A good portion of the power consumed by FPGA can be avoided, as about three quarters of the dynamic power consumed by FPGAs could be ascribed to glitches rather than actual functional state transitions for some types of circuits [11].FPGA users can only optimize the dynamic power component of the overall power consumed by the FPGA, that is dependent upon the value of capacitance, switching frequency, and power supply voltage of each circuit node[9].

To understand sources of power dissipation in FPGAs in real sense and to develop low-power FPGA based designs, it is essential to understand and develop accurate power model of FPGA that may be helpful to application designers to ensure that their applications meet various power budgets. Power-aware FPGA CAD tools require detailed power estimates to reduce and optimize power consumption. Above all, development of power-efficient FPGA architecture, CAD tools and various low-power FPGA based techniques depend mainly upon accurate power estimation and power-modeling of FPGA.

Techniques to Reduce Power Consumption

The following are some useful techniques that may be used to reduce power consumption in FPGAs:

• Low Power System Level Design Techniques
• Device Level Design Techniques
• Circuit and Architecture Level Design Techniques
• Utilization of Low Power FPGA CAD Tools

These techniques are discussed in detail below.

 Low Power System Level Design Techniques:Low Power System Level Design Techniques involve those techniques that have been employed by application developers to reduce power consumption in currently available FPGAs. These techniques may be classified into three categories: basic techniques, techniques involving run-time re-configurability and techniques for software processors [1].

Basic Techniques: Using coarse-grained logic blocks, which are more power-efficient than fine-grained logic blocks, may help reduce power consumption in FPGAs provided that the power consumption for routing is managed to be kept under control. Glitches, which constitute a significant portion of the dynamic power dissipation, may be reduced by using Pipelining. It has been observed that at a given clock frequency, pipelining may result in 40 to 90 percent reduction in energy per operation. Word length optimization can lead to best trade-off in speed, area, power consumption, flexibility and accuracy. Dynamic power consumption may be reduced by using clock gating. In clock gating, clock is disabled for inactive regions thus preventing the signal transitions that result in power consumption. Clock gating combined with word-length optimization can help reduce power consumption more effectively than utilizing either of these techniques individually. Dynamic voltage scaling to adapt the supply voltage to FPGA with temperature variations may help reduce power consumption. Using this technique 4 to 54 percent reduction in power consumption may be achieved for various arithmetic circuits.

Techniques involving Run time Re-configurability: To adopt the smallest design at a given time, word-length optimization can be combined with runtime reconfiguration provided that the energy overhead for reconfiguration is less than the energy reduction in execution. To change a design, in real-time applications, for adapting to run-time conditions, run-time reconfiguration may be applied to an FPGA based system.

Techniques for Soft Processors: As low power techniques for FPGA-based soft processors, instruction set extensions to MicroBlaze soft processor, based on iterative improvement method, have been proposed in [12]. Using this technique up to40% reduction in energy and 12% reduction in peak power have been reported [1].To optimize soft-processor at multiple levels of abstraction, combined application of instruction recoding techniques and power-aware rescheduling may be employed [1]. Using these techniques power reduction of up to 74% has been reported in [13].

 Device Level Design Techniques:As we move into deep sub-micron geometries, increases in functionality per square millimeter come at cost of higher static power consumption due to higher transistor leakage [44].To reduce and optimize power consumption, latest FPGA devices from leading FPGA vendors like Xilinx and Altera have incorporated various low power device-level techniques, which are being discussed in this section. To trade-off between performance and static power consumption, unlike earlier technologies where only two gate thicknesses were available at device level, both Altera and Xilinx utilize triple gate oxide technology [1].This technique  provides a choice of three different gate thicknesses, where transistors with thicker oxide are used for large, higher voltage tolerant transistors in the I/O blocks, while thinner ones are used elsewhere with low voltage requirements, while medium thickness oxide transistors, with slightly less performance but significantly less leakage current than thin oxide transistors, are used in configuration memory and the switches controlled by this memory. Since the configuration memory remains static during the operation of the device, the oxide thickness does not affect the performance of corresponding switches [1].To reduce the parasitic capacitance, which is a major source of dynamic power dissipation, the FPGA vendors use low-k dielectric between metal layers and use small device geometries. The dynamic power of the core FPGAs, due to having quadratic relationship (CV²f) with the supply voltage, may be further reduced by lowering the supply voltage. In this design approach, the core supply voltage may be selected by the user according to the performance requirements of the system. FPGA Vendors like Xilinx and Altera have incorporated this design technique in their latest FPGAs, where performance requirements are high the user may select a higher voltage, while for low power consumption requirements, lower core supply voltage may be selected. Supplying the FPGA Core voltage at the lower limit of manufacturer’s specification can save significant static power [44].Small increases in core voltages can lead to large increases in static power [44].Conversely, a low core voltage can lower dynamic power consumption [44].At architecture level, power consumption may be reduced further by increasing the size of LUTs (Lookup Tables) within the logic blocks. This design approach reduces both static and dynamic power as more logic is implemented in each LUT and less routing is required between LUTs. LUTs are implemented with smaller transistors as compared with the transistors used in routing resources that result in reduced dynamic power dissipation and less leakage current. If routing architecture is modified to increase the number of 1-hop routes, this will result in reduction in average capacitance of routes that will improve both power consumption and performance. This design approach has been adopted by both Xilinx and Altera. Other architecture level design features that may be adopted to improve power consumption include the use of embedded memories, adders, multipliers and ALUs, which can be turned off when not needed. A number of low power techniques can be implemented through FPGA CAD tools by integrating detailed power models of FPGAs within the commercial FPGA CAD tools. This technique has been adopted by both Xilinx and Altera, by providing a spreadsheet utility in their CAD tools to make early power predictions before completion of design and by incorporating detailed power models in their CAD tools which may be used when the design has been completed. The early power estimates are based on the estimated resource usage, I/O types, clock frequencies, clock requirements and environmental conditions [1].The detailed power models provide more accurate estimates than early power models, which are used to estimate power after the application has been placed, routed and simulated, as all the requisite information to estimate the power is available in detailed power models. Power aware CAD techniques, that involve reducing capacitance of high activity signals during placement, routing and technology mapping, have also been provided by some vendors in their CAD tools. Power may also be minimized by mapping to embedded memories [14], and by optimizing the mapping to DSP blocks [1].To reduce power consumption unused resources in FPGAs should be turned off this is what CAD tools provided by both renowned FPGA vendors Xlinx and Altera are equipped with. To reduce power, low power flash-based FPGA technology may be used instead of SRAM-based FPGAs.

 Circuit- and Architecture-Level Design Techniques:The circuit and architecture level design techniques involve manipulating mapping applications to FPGA resources and circuitry to implement these resources. That’s why these techniques play a major role in power reduction and optimization in FPGAs. To reduce power through these techniques, a low power FPGA architecture design needs to be developed. Such design techniques have been described in [15] [16], which propose developing energy-efficient FPGA routing architectures and use of low-swing signaling techniques. A new FPGA architecture that uses a combination of hardwired and traditional programmable switches is proposed in [17], which reduces the number of routing elements to lower static and dynamic power. To reduce power being lost to the logic not in use, a novel FPGA routing switch has been proposed in [18]. It is a high speed and low power switch with sleep mode, which reduces dynamic power for non-timing critical logic and standby power for logic not in use. According to the technique proposed in [19], static power may be reduced by applying power gating to the switches in routing resources, while dynamic power may be reduced by using duplicate routing resources that use either low or high Vdd. In [20], energy-efficient modules for embedded components in FPGAs have been introduced. According to this technique, power consumption in FPGA may be reduced by optimizing the number of connections between the routing resources and the module, and by using reduced supply voltage circuit techniques. Several power reduction techniques have been proposed for coarse-grain cell-based architecture in [21].These techniques include register file elimination and efficient instruction fetch.

These above mentioned techniques have been proved to be quite effective in reducing power consumption in FPGA; further improvements in this regard may be achieved by reducing glitches and by having an efficient FPGA clock network design.  

Glitches constitute a major source of power consumption in FPGAs. According to a study presented in [23], a simulation of a fully combination 32-bit shift & add multiplier shows that glitches represent 80% of the activity. Glitches occur when values at inputs of a LUT toggle at different times due to due to uneven propagation delays of those signals [1].If the arrival times are far enough apart, spurious transitions can be produced at the LUT output [1].Glitches can be reduced in several ways: A list of techniques is summarized in table 1 [23] below:

Table 1 [23]: Techniques to reduce glitch-power in FPGAs

Clock networks play a major role in FPGA power consumption. Since the clock networks connect to each flip-flop and toggle every clock cycle, so efficient and low-power clock network design is an important technique in bringing about significant reduction in power consumption. In [4], the clock network in FPGA is said to account for 19% of dynamic power. Placement of applications within FPGA is affected by the constraints imposed by clock networks and these constraints depend upon how flexible clock network is. In [24][25],a parameterized framework for a wide range of clock networks, clock-aware placement techniques and experiments to make FPGA clock networks more efficient have been proposed.

 Low Power FPGA CAD Techniques:It is also possible to reduce power without incurring any costly hardware or process changes. Power issues can be tackled through power-driven CAD algorithms and design flows [47].The FPGA CAD tools map an application to FPGA programmable fabric. Important advancements have been made in FPGA CAD tools that help reduce power consumption.  These CAD tools may prove to be quite effective in reducing power consumption in FPGAs. This mapping process may be divided into five stages [1]:high-level synthesis, technology mapping, clustering, placement and routing. Optimizing each stage of this mapping process individually may bring about significant improvement in final implementation. The FPGA CAD tools from leading vendors like Xilinx and Altera are equipped with many advanced algorithms for power efficient placement and routing of digital logic design implemented on FPGAs.

According to the technique proposed in [26], reduction in power consumption is achieved by minimizing total power of operations and multiplexers that connect them. The power reduction technique described in [27] focuses on FPGAs with programmable power supplies and proposes connecting low-Vdd to as many operations as possible provided that resources and timing constraints are met. According to low-power technology mapping algorithms proposed in [28][29][30][31][32][33][34][35],power consumption may be minimized by absorbing as many high-activity nodes as possible when gates are packed into LUTs and/or by minimizing the node duplication. Node-duplication increases the amount of interconnect between LUTs. Low power clustering techniques described in [36][37][32][38],propose reducing power by absorbing as many small and high-activity nets as possible when the LUTs are packed into clusters. The number of Inter-cluster nets, which dissipate the most power, may be reduced by absorbing small nets. Further reduction in power consumption is possible through absorbing high-activity nets. Low power place and route techniques described in [39][32][40][41],propose that power may be reduced by minimizing the distance between logic blocks connected by high-activity wires and by routing the high-activity wires as directly as possible. Minimizing the leakage power may reduce power consumption, which according to [42] may be minimized by choosing low-leakage LUT configurations. According to power-aware algorithms, for mapping logical memories to physical memories in FPGA embedded memories, described in [43], dynamic power may be reduced by evaluating a range of possible mappings and selecting the most power-efficient choice. Also care must be taken while writing HDL code. Implement technique like one-hot encoding for state-machines and guarded evaluation while making sure you don’t inadvertently create logic loops that oscillate [44].  

Acknowledgement : The core idea of this article is based on [1].

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