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This blog post was previously titled MyHDL ASIC Proven (How is this related to FPGAs?) but the blog post has been updated and mainly discusses developing FPGA-DSP IP with Python / MyHDL. The original content is still present but the post has been reorganized and expanded. Original post 16-Mar-2010.
Using Python to develop DSP logic for an FPGA is very powerful. The Python ecosystem contains many packages including numerical and scientific packages. Numpy and Scipy are two of the more popular packages available. With Numpy and Scipy signal processing design and analysis is possible in the Python language. Combining the signal processing tools and HDL into a single environment is awesome.
Many commercial products have attempts at combining these worlds but most try to bring the numeric computing to existing HDL tools (e.g. driving HDL simulation). In contrast the Python ecosystem provides a single unified environment. Python has other EDA packages including SPICE integration with eispice. The SPICE engine and HDL allow mixed-signal simulation from the Python environment.
MyHDL is an HDL implementation in Python and is an RTL similar to Verilog and VHDL. MyHDL adds a hardware description language to the Python ecosystem! I was first introduced to MyHDL around 2004 by a colleague from an article he had read in the Linux Journal. After some time I started actively following the project and later I made minor contributions to the project. Contributions have mainly been project postings in the project user space and some minor patches.
The goal of the MyHDL project is to empower hardware designers with the elegance and simplicity of the Python language. MyHDL is a free, open-source package using Python as a hardware description and verification language. There's a ton of information on the MyHDL website, see Why MyHDL for some of the reasons why one should consider using MyHDL. The site also has several FPGA projects and examples.
Additional reasons why:
Jan Decaluwe posted information about an ASIC design where the digital portion was designed, implemented, and verified in MyHDL, see MyHDL Digital Macro for more information.
The MyHDL first ASIC design is pertinent to HDL developers, FPGA and ASIC alike, because it shows the maturity of the MyHDL language / tool.
To illustrate the power of Python / MyHDL a simple IIR filter object was created. The object, SIIR, will be used to define the IIR filter (define the response), configure the HDL, verify the HDL, and generate the synthesizable HDL.
SIIR basic usage example:
In : flt = siir.SIIR(Fc=1333, Fs=48000) IIR w,b,a 0.0555416666667 [ 0.00676222 0.01352445 0.00676222] [ 1. -1.7542798 0.78132869] IIR fixed-point b,a (56726, 113451, 56726) (8388608, -14715966, 6554260) In : plot(flt.hz, 20*log10(abs(flt.h))) Out:  In : tb = flt.TestFreqResponse(Nloops=128, Nfft=1024) In : from myhdl import Simulation In : Simulation(tb).run() In : flt.PlotResponse() In : show()
The following is the MyHDL description for the digital hardware implementation of a second order type I IIR filter. The MyHDL version should look familiar to most digital hardware designers because MyHDL is a register transfer language (RTL). Even if the MyHDL syntax is unfamiliar the general concept is similar to Verilog and VHDL. The language has direct control of the hardware organization. MyHDL is not a higher-level synthesis tool.
@always(clk.posedge) def rtl_iir(): if ts: ffd.next = ffd ffd.next = x fbd.next = fbd fbd.next = yacc[Qd:self.Q].signed() # An additional clock delay but not Ts (sample rate) delay. y.next = yacc[Qd:self.Q].signed() @always_comb def rtl_acc(): # Double precision accumulator yacc.next = (b0*x) + (b1*ffd) + (b2*ffd) - (a1*fbd) - (a2*fbd)
The above behavioral description is a direct implementation of the difference equation for a direct form I IIR filter. In other-words, this is a straight forward hardware implementation and would require five multiplies and four additions. Nothing special has been done to optimize the hardware.
This single class allows the definition of the IIR filter (filter response) and the creation of the hardware based on the filter design. This code snippet illustrates how to use the class object for this simple IIR filter. The class object provides a means to define the filters frequency response and create the HDL. The complete source code is available on BitBucket.
Running a simulation on the HDL IIR filter produces the Figure 3 response. This is where the power of the Python ecosystem shines. It is straight-forward to simultaneously simulate the floating-point response and the HDL response. The filter can be verified and analyzed.
Synthesizing the generated Verilog produces the following results for a Xilinx XC3S500E part.
Python and MyHDL are very powerful. An FPGA-DSP design can be fully defined in a single language. Different languages and tools are not required. The Python ecosystem allows a designer to leverage a flexible language for all the steps required in developing DSP IP for an FPGA.
|||R. Lyons, "Understanding Digital Signal Processing", 2nd ed., Prentice Hall, Upper Saddle River, New Jersey, 2004|
Last updated 2011-08-24
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