Conditional Interpretation of VHDL

Gabor <gabor@szakacs.org> wrote:

(snip, I wrote)
>> The one that keeps bothering me, is that you can't have lines in
>> the UCF file for ports you aren't using.
 
> You can certainly leave constraints for unused ports in Xilinx tools.
> There's a couple of command line options, -aul and -aut IIRC to allow
> unmatched LOC constraints and unmatched timing constraints.  In some
> versions of ISE, you can place all constraints for a port, LOC, IO
> Standard, Slew, Pullup, etc. on one line using | between constraints
> and the -aul will ignore the full line.  In other versions the -aul
> just ignores some of the constraints and errors out on others.
> Oh, well...

So far, I use the GUI, but sometime should switch to the
command line version.  Maybe the GUI allows it, too, but I
didn't see where.

-- glen

Gabor <gabor@szakacs.org> wrote:
> On 6/23/2015 4:08 PM, glen herrmannsfeldt wrote:
> > Theo Markettos <theom+news@chiark.greenend.org.uk> wrote:
> >
> >> Let's say I change my PCIe port from 4x to 1x, which is a simple
> >> dropdown on the PCIe core.  If I have the ports on my toplevel module,
> >> but don't connect them to anything, I get an error.  If I remove the
> >> ports from my toplevel module, but leave the transceiver settings
> >> alone, it compiles.
> 
> A standard way to do this without `ifdef is to make the ports vectors
> and use a parameter to define the port width.  At least that's how the
> xilinx cores do it, and it works for either VHDL or Verilog.  It's
> a bit clunky to refer to a lane as TXn[3] / TXp[3] (one bit slice
> of each of two "vectors" to make a differential pair) but it works.

That works if I'm changing the width of a port, but what if I'm not using
PCIe at all today?  I don't believe you can do:

`parameter PCIE_WIDTH -1

output [`PCIE_WIDTH:0] PCIE_TX_p;

and hope that it'll delete PCIE_TX_p completely.

> You can certainly leave constraints for unused ports in Xilinx tools.
> There's a couple of command line options, -aul and -aut IIRC to allow
> unmatched LOC constraints and unmatched timing constraints.  In some
> versions of ISE, you can place all constraints for a port, LOC, IO
> Standard, Slew, Pullup, etc. on one line using | between constraints
> and the -aul will ignore the full line.  In other versions the -aul
> just ignores some of the constraints and errors out on others.
> Oh, well...

Most of the time this works for Altera too, it's the case of transceivers
where it doesn't.  I have no idea why, it's arguably a bug in the tools.

The tools don't like partitions or LogicLock regions which aren't
associated with logic, but that's more likely to be a bug that you want to
be alerted of.  It's a pain when the list of modules in your design is
configurable, though.

Theo

glen herrmannsfeldt wrote:
> Gabor <gabor@szakacs.org> wrote:
> 
> (snip, I wrote)
>>> The one that keeps bothering me, is that you can't have lines in
>>> the UCF file for ports you aren't using.
>  
>> You can certainly leave constraints for unused ports in Xilinx tools.
>> There's a couple of command line options, -aul and -aut IIRC to allow
>> unmatched LOC constraints and unmatched timing constraints.  In some
>> versions of ISE, you can place all constraints for a port, LOC, IO
>> Standard, Slew, Pullup, etc. on one line using | between constraints
>> and the -aul will ignore the full line.  In other versions the -aul
>> just ignores some of the constraints and errors out on others.
>> Oh, well...
> 
> So far, I use the GUI, but sometime should switch to the
> command line version.  Maybe the GUI allows it, too, but I
> didn't see where.
> 
> -- glen

In the GUI you go to translate properties --> "Other NGDBuild
command line options" and there you can add any options you
want.  However more recent versions of the GUI have -aul
and -aut as check boxes as well.

-- 
Gabor

Gabor wrote:
>> The one that keeps bothering me, is that you can't have lines in
>> the UCF file for ports you aren't using.
>>
> You can certainly leave constraints for unused ports in Xilinx tools.
> There's a couple of command line options, -aul and -aut IIRC to allow
> unmatched LOC constraints and unmatched timing constraints.  In some
> versions of ISE, you can place all constraints for a port, LOC, IO
> Standard, Slew, Pullup, etc. on one line using | between constraints
> and the -aul will ignore the full line.  In other versions the -aul
> just ignores some of the constraints and errors out on others.
> Oh, well...

<rant>
I never got why the DEFAULT behaviour is to quit with an error when
there's LOC constraints for non-existant ports, but only issue a warning
(which easily gets lost amongst thousands others in the logs) if an
existing port is NOT location constrained.
The tool then places the IO randomly, and this is most certainly not the
desired behaviour, since you could potentially damage hardware when
you're driving an IO that connects to something that should not be
driven. Unlikely, but possible.

The only exception I can think of is in the hardware concept phase, when
you want to let the tools chose a valid pin out for you that you can
then copy to your schematic. But that is a rare case that IMHO would
justify an extra mouse click or an added command line switch.

This DEFAULT behaviour is stupid IMHO. Of course you can change it with
obscure command-line switches or a setting hidden away in some
"Advanced" tab, but someone at Xilinx must have deliberately chosen to
make this the default behaviour for whatever reason, and I don't get it.
I think this is one of these things that got introduced in a very early
software release, and even though it doesn't make any sense at all, it
was never fixed because people would get confused if the default
behaviour changed.

I think Vivado now issues a "Critical Warning" by default for
unconstrained ports.
Sounds better, but when you think about it, it doesn't help a lot, since
critical warnings also do not stop the flow (unless you promote that
warning to an error).
Unless you use the GUI, those critical warnings can also easily get lost
in the log files if you don't specifically look for them, especially
when you use a purely command-line driven flow like me.

Not to mention that I don't understand what the hell a "Critical
Warning" is supposed to be. Either it's a warning, or it's critical, and
then it'd better be an error. What sense does it make to introduce
another severity level in between "warning" and "error"? I personally
have not seen a "critical warning" that did not cause me to re-run the
entire flow, and then it would have been better to stop the flow right
the moment the critical warning occured as not to waste my time. That's
why I've promoted all critical warning to errors, which fortunately is
easy enough in Vivdao via Tcl.

</rant>,
Sean

GaborSzakacs <gabor@alacron.com> wrote:

(snip on ignoring UCF entries for pins that don't exist.)

>> So far, I use the GUI, but sometime should switch to the
>> command line version.  Maybe the GUI allows it, too, but I
>> didn't see where.
 
> In the GUI you go to translate properties --> "Other NGDBuild
> command line options" and there you can add any options you
> want.  However more recent versions of the GUI have -aul
> and -aut as check boxes as well.

OK, I did that.

Thanks!

This is especially useful for starter boards which have a lot of
pins that you aren't using, but also for general purpose boards,
again with extra pins that you might not be using.

-- glen