Correlator of a big antenna array on FPGA

On 10/3/2015 3:42 PM, Kevin Neilson wrote:
> I've had to work at the low end, where the part is always full and I have to fake multiplication with lookup tables.  Now I'm at the other end, where the volumes are low and the customer doesn't care about FPGA price so the parts are huge.  They must cost a fortune.  I still waste a lot of time of PAR issues, but it's wonderful having more gates, DSPs, and blockRAMs than I could ever need.

Personally I enjoy the challenge of fitting tight designs.  To me trying 
to get a part to meet timing is not as much fun as getting a part to fit 
the device.  I find timing analysis to be very tedious as you get 
literally hundreds of failed path reports from what is basically the 
same endpoints, just many variations.  This makes it hard to see the 
next longer path that is also failing.  Reminds me of debugging a 
program one mistake at a time in the old days when my first pass would 
have many bugs... and the new days too sometimes.   lol

Fitting can have very interesting tradeoffs.  Often they are algorithmic 
and require learning new ways of calculating results.  I find that very 
interesting.

-- 

Rick