Hello i am new in vhdl, but try it, I want to make pipe between OV7670 and monitor, best thing is to use code of Hamsterwork's with Lauri's edition http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_OV7670 and http://lauri.v�sandi.com/hdl/zynq/zybo-ov7670-to-vga.html and want to adopt it to ML402 for Virtex-4 XC4VSX35, it requires 8 bit for each color in RGB,and bram address can be only 18bit wide, i made edition but cannot get any picture, link to this video on youtube https://youtu.be/Tr-9UzEL-D8 code i modified, top_level, capture, vga, memory, clocking http://download.files.namba.kg/files/147527022 pass :'123' could someone help to check for video and code , what problem with which signal ?
hamsterworks + lauriVosandi + X = Error
Started by ●January 5, 2016
Reply by ●January 5, 20162016-01-05
On 1/5/2016 6:44 AM, abirov@gmail.com wrote:> Hello i am new in vhdl, but try it, > I want to make pipe between OV7670 and monitor, best thing is to use code of Hamsterwork's with Lauri's edition > http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_OV7670 and > http://lauri.v�sandi.com/hdl/zynq/zybo-ov7670-to-vga.html and want to adopt it to ML402 for Virtex-4 XC4VSX35, it requires 8 bit for each color in RGB,and bram address can be only 18bit wide, i made edition but cannot get any picture, link to this video on youtube > https://youtu.be/Tr-9UzEL-D8 > code i modified, top_level, capture, vga, memory, clocking > > http://download.files.namba.kg/files/147527022 pass :'123' > > could someone help to check for video and code , what problem with which signal ?Have you tried running this in a simulator? Did you create timing constraints and use the timing analysis tool? -- Rick
Reply by ●January 6, 20162016-01-06
> Have you tried running this in a simulator? Did you create timing > constraints and use the timing analysis tool?I do not know how to do it, I will route it and use oscilloscope
Reply by ●January 6, 20162016-01-06
On 1/6/2016 1:35 AM, abirov@gmail.com wrote:>> Have you tried running this in a simulator? Did you create timing >> constraints and use the timing analysis tool? > > I do not know how to do it, I will route it and use oscilloscopeYou need to learn how to design FPGAs properly. A simulator is not hard to use. Most of the work is in writing a VHDL test bench to properly exercise your design. The timing analysis tool lets you specify the timing required in your design such as clock cycle times, time from signal input to the clock and from the clock to signal outputs. Trying to do this with an oscilloscope is nearly impossible for any internal signals. The timing analysis tool lets you do this as part of your design process without loading the design onto your board. -- Rick
Reply by ●January 6, 20162016-01-06
On 06/01/16 06:35, abirov@gmail.com wrote:>> Have you tried running this in a simulator? Did you create timing >> constraints and use the timing analysis tool? > > I do not know how to do it, I will route it and use oscilloscopeIf you haven't tested the design before routing then there is no reason to believe your circuit does what you would like it to do. If you haven't tested the design after place and route then there is no reason to believe you specified your system requirements correctly, nor that the tool satisfied the unstated requirements (naturally!), nor even that it was able to satisfy the stated requirements.
Reply by ●January 6, 20162016-01-06
--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
D:\xilinx_core\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3
-s 12 -n 3 -fastpaths -xml ov7670_top_preroute.twx ov7670_top_map.ncd -o
ov7670_top_preroute.twr ov7670_top.pcf -ucf constraint.ucf
Design file: ov7670_top_map.ncd
Physical constraint file: ov7670_top.pcf
Device,package,speed: xc4vsx35,ff668,-12 (PRODUCTION 1.71 2013-10-13, STEPPING level 1)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock OV7670_PCLK
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
OV7670_D<0> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<1> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<2> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<3> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<4> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<5> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<6> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<7> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_HREF | -0.353(R)| 0.912(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_VSYNC| 0.259(R)| 0.852(R)|OV7670_PCLK_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock clk100
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
btn | 2.830(R)| -2.133(R)|clk50 | 0.000|
------------+------------+------------+------------------+--------+
Clock clk100 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
Nblank | 2.358(R)|clk25 | 0.000|
OV7670_SIOC | 2.066(R)|clk50 | 0.000|
OV7670_SIOD | 2.358(R)|clk50 | 0.000|
OV7670_XCLK | 2.066(R)|clk50 | 0.000|
led | 2.358(R)|clk50 | 0.000|
vga_blue<0> | 2.066(R)|clk25 | 0.000|
vga_blue<1> | 2.066(R)|clk25 | 0.000|
vga_blue<2> | 2.066(R)|clk25 | 0.000|
vga_blue<3> | 2.066(R)|clk25 | 0.000|
vga_blue<4> | 2.066(R)|clk25 | 0.000|
vga_blue<5> | 2.066(R)|clk25 | 0.000|
vga_blue<6> | 2.066(R)|clk25 | 0.000|
vga_blue<7> | 2.066(R)|clk25 | 0.000|
vga_green<0>| 2.066(R)|clk25 | 0.000|
vga_green<1>| 2.066(R)|clk25 | 0.000|
vga_green<2>| 2.066(R)|clk25 | 0.000|
vga_green<3>| 2.066(R)|clk25 | 0.000|
vga_green<4>| 2.066(R)|clk25 | 0.000|
vga_green<5>| 2.066(R)|clk25 | 0.000|
vga_green<6>| 2.066(R)|clk25 | 0.000|
vga_green<7>| 2.066(R)|clk25 | 0.000|
vga_hsync | 2.066(R)|clk25 | 0.000|
vga_red<0> | 2.066(R)|clk25 | 0.000|
vga_red<1> | 2.066(R)|clk25 | 0.000|
vga_red<2> | 2.066(R)|clk25 | 0.000|
vga_red<3> | 2.066(R)|clk25 | 0.000|
vga_red<4> | 2.066(R)|clk25 | 0.000|
vga_red<5> | 2.066(R)|clk25 | 0.000|
vga_red<6> | 2.066(R)|clk25 | 0.000|
vga_red<7> | 2.066(R)|clk25 | 0.000|
vga_vsync | 2.066(R)|clk25 | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock OV7670_PCLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
OV7670_PCLK | 1.543| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk100
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk100 | 3.571| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
clk100 |clkout | 1.808|
---------------+---------------+---------+
Analysis completed Wed Jan 06 16:51:22 2016
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 330 MB
Reply by ●January 8, 20162016-01-08
On Wednesday, January 6, 2016 at 4:09:15 PM UTC+6, Tom Gardner wrote:> On 06/01/16 06:35, abirov@gmail.com wrote: > >> Have you tried running this in a simulator? Did you create timing > >> constraints and use the timing analysis tool? > > > > I do not know how to do it, I will route it and use oscilloscope > > If you haven't tested the design before routing then there > is no reason to believe your circuit does what you would > like it to do. > > If you haven't tested the design after place and route then > there is no reason to believe you specified your system > requirements correctly, nor that the tool satisfied the > unstated requirements (naturally!), nor even that it was > able to satisfy the stated requirements.All values displayed in nanoseconds (ns) Setup/Hold to clock OV7670_PCLK ------------+------------+------------+------------------+--------+ |Max Setup to|Max Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ OV7670_D<0> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000| OV7670_D<1> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| OV7670_D<2> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000| OV7670_D<3> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| OV7670_D<4> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| OV7670_D<5> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| OV7670_D<6> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| OV7670_D<7> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000| OV7670_HREF | -0.353(R)| 0.912(R)|OV7670_PCLK_BUFGP | 0.000| OV7670_VSYNC| 0.259(R)| 0.852(R)|OV7670_PCLK_BUFGP | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock clk100 ------------+------------+------------+------------------+--------+ |Max Setup to|Max Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ btn | 2.830(R)| -2.133(R)|clk50 | 0.000| ------------+------------+------------+------------------+--------+ Clock clk100 to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ Nblank | 2.358(R)|clk25 | 0.000| OV7670_SIOC | 2.066(R)|clk50 | 0.000| OV7670_SIOD | 2.358(R)|clk50 | 0.000| OV7670_XCLK | 2.066(R)|clk50 | 0.000| led | 2.358(R)|clk50 | 0.000| vga_blue<0> | 2.066(R)|clk25 | 0.000| vga_blue<1> | 2.066(R)|clk25 | 0.000| vga_blue<2> | 2.066(R)|clk25 | 0.000| vga_blue<3> | 2.066(R)|clk25 | 0.000| vga_blue<4> | 2.066(R)|clk25 | 0.000| vga_blue<5> | 2.066(R)|clk25 | 0.000| vga_blue<6> | 2.066(R)|clk25 | 0.000| vga_blue<7> | 2.066(R)|clk25 | 0.000| vga_green<0>| 2.066(R)|clk25 | 0.000| vga_green<1>| 2.066(R)|clk25 | 0.000| vga_green<2>| 2.066(R)|clk25 | 0.000| vga_green<3>| 2.066(R)|clk25 | 0.000| vga_green<4>| 2.066(R)|clk25 | 0.000| vga_green<5>| 2.066(R)|clk25 | 0.000| vga_green<6>| 2.066(R)|clk25 | 0.000| vga_green<7>| 2.066(R)|clk25 | 0.000| vga_hsync | 2.066(R)|clk25 | 0.000| vga_red<0> | 2.066(R)|clk25 | 0.000| vga_red<1> | 2.066(R)|clk25 | 0.000| vga_red<2> | 2.066(R)|clk25 | 0.000| vga_red<3> | 2.066(R)|clk25 | 0.000| vga_red<4> | 2.066(R)|clk25 | 0.000| vga_red<5> | 2.066(R)|clk25 | 0.000| vga_red<6> | 2.066(R)|clk25 | 0.000| vga_red<7> | 2.066(R)|clk25 | 0.000| vga_vsync | 2.066(R)|clk25 | 0.000| ------------+------------+------------------+--------+ Clock to Setup on destination clock OV7670_PCLK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ OV7670_PCLK | 1.543| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock clk100 ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk100 | 3.571| | | | ---------------+---------+---------+---------+---------+ Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ clk100 |clkout | 1.808| ---------------+---------------+---------+ Analysis completed Wed Jan 06 16:51:22 2016 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 330 MB Could someone help to me ??????????? Guys???
Reply by ●January 9, 20162016-01-09
On Fri, 08 Jan 2016 19:50:49 -0800, abirov wrote:> On Wednesday, January 6, 2016 at 4:09:15 PM UTC+6, Tom Gardner wrote: >> On 06/01/16 06:35, abirov@gmail.com wrote: >> >> Have you tried running this in a simulator? Did you create timing >> >> constraints and use the timing analysis tool? >> > >> > I do not know how to do it, I will route it and use oscilloscope >> >> If you haven't tested the design before routing then there is no reason >> to believe your circuit does what you would like it to do. > > Could someone help to me ??????????? Guys???You have already been given helpful advice. Simulate, get it working in simulation. It's your choice to use or ignore that advice, that's not our problem. -- Brian
Reply by ●January 9, 20162016-01-09
On 1/8/2016 10:50 PM, abirov@gmail.com wrote:> On Wednesday, January 6, 2016 at 4:09:15 PM UTC+6, Tom Gardner wrote: >> On 06/01/16 06:35, abirov@gmail.com wrote: >>>> Have you tried running this in a simulator? Did you create timing >>>> constraints and use the timing analysis tool? >>> >>> I do not know how to do it, I will route it and use oscilloscope >> >> If you haven't tested the design before routing then there >> is no reason to believe your circuit does what you would >> like it to do. >> >> If you haven't tested the design after place and route then >> there is no reason to believe you specified your system >> requirements correctly, nor that the tool satisfied the >> unstated requirements (naturally!), nor even that it was >> able to satisfy the stated requirements. > > All values displayed in nanoseconds (ns) > > Setup/Hold to clock OV7670_PCLK > ------------+------------+------------+------------------+--------+ > |Max Setup to|Max Hold to | | Clock | > Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | > ------------+------------+------------+------------------+--------+ > OV7670_D<0> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<1> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<2> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<3> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<4> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<5> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<6> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<7> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_HREF | -0.353(R)| 0.912(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_VSYNC| 0.259(R)| 0.852(R)|OV7670_PCLK_BUFGP | 0.000| > ------------+------------+------------+------------------+--------+ > > Setup/Hold to clock clk100 > ------------+------------+------------+------------------+--------+ > |Max Setup to|Max Hold to | | Clock | > Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | > ------------+------------+------------+------------------+--------+ > btn | 2.830(R)| -2.133(R)|clk50 | 0.000| > ------------+------------+------------+------------------+--------+ > > Clock clk100 to Pad > ------------+------------+------------------+--------+ > | clk (edge) | | Clock | > Destination | to PAD |Internal Clock(s) | Phase | > ------------+------------+------------------+--------+ > Nblank | 2.358(R)|clk25 | 0.000| > OV7670_SIOC | 2.066(R)|clk50 | 0.000| > OV7670_SIOD | 2.358(R)|clk50 | 0.000| > OV7670_XCLK | 2.066(R)|clk50 | 0.000| > led | 2.358(R)|clk50 | 0.000| > vga_blue<0> | 2.066(R)|clk25 | 0.000| > vga_blue<1> | 2.066(R)|clk25 | 0.000| > vga_blue<2> | 2.066(R)|clk25 | 0.000| > vga_blue<3> | 2.066(R)|clk25 | 0.000| > vga_blue<4> | 2.066(R)|clk25 | 0.000| > vga_blue<5> | 2.066(R)|clk25 | 0.000| > vga_blue<6> | 2.066(R)|clk25 | 0.000| > vga_blue<7> | 2.066(R)|clk25 | 0.000| > vga_green<0>| 2.066(R)|clk25 | 0.000| > vga_green<1>| 2.066(R)|clk25 | 0.000| > vga_green<2>| 2.066(R)|clk25 | 0.000| > vga_green<3>| 2.066(R)|clk25 | 0.000| > vga_green<4>| 2.066(R)|clk25 | 0.000| > vga_green<5>| 2.066(R)|clk25 | 0.000| > vga_green<6>| 2.066(R)|clk25 | 0.000| > vga_green<7>| 2.066(R)|clk25 | 0.000| > vga_hsync | 2.066(R)|clk25 | 0.000| > vga_red<0> | 2.066(R)|clk25 | 0.000| > vga_red<1> | 2.066(R)|clk25 | 0.000| > vga_red<2> | 2.066(R)|clk25 | 0.000| > vga_red<3> | 2.066(R)|clk25 | 0.000| > vga_red<4> | 2.066(R)|clk25 | 0.000| > vga_red<5> | 2.066(R)|clk25 | 0.000| > vga_red<6> | 2.066(R)|clk25 | 0.000| > vga_red<7> | 2.066(R)|clk25 | 0.000| > vga_vsync | 2.066(R)|clk25 | 0.000| > ------------+------------+------------------+--------+ > > Clock to Setup on destination clock OV7670_PCLK > ---------------+---------+---------+---------+---------+ > | Src:Rise| Src:Fall| Src:Rise| Src:Fall| > Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| > ---------------+---------+---------+---------+---------+ > OV7670_PCLK | 1.543| | | | > ---------------+---------+---------+---------+---------+ > > Clock to Setup on destination clock clk100 > ---------------+---------+---------+---------+---------+ > | Src:Rise| Src:Fall| Src:Rise| Src:Fall| > Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| > ---------------+---------+---------+---------+---------+ > clk100 | 3.571| | | | > ---------------+---------+---------+---------+---------+ > > Pad to Pad > ---------------+---------------+---------+ > Source Pad |Destination Pad| Delay | > ---------------+---------------+---------+ > clk100 |clkout | 1.808| > ---------------+---------------+---------+ > > > Analysis completed Wed Jan 06 16:51:22 2016 > -------------------------------------------------------------------------------- > > Trace Settings: > ------------------------- > Trace Settings > > Peak Memory Usage: 330 MB > > Could someone help to me ??????????? Guys???Others have explained that you will debug the logic of your design much more easily in a simulation than on the bench. Debugging in the chip is hard because you need to bring signals out to see what his happening. The simulator allows you to view any signal at any time. You can get waveform displays, or probe signals in a list showing the current value. You can even walk through the code with breakpoints if that is how you like to do it (I never use this but others do). Then, once you have the logic working correctly you can deal with timing issues. To use the timing analysis you need to create timing constraints. These constraints consist of clock period (or frequency), input clock setup times and output delay times. If you don't understand what these timing constraints mean then you need to ask questions. Just posting part of a timing report and saying "help" isn't the way to get useful help. Here is a pointer. In your previous post the tool gives you one very important error message.... INFO:Timing:2698 - No timing constraints found, doing default enumeration. -- Rick
Reply by ●January 19, 20162016-01-19
