How to define multi-cycle timing constraints in Lattice iCEcube2 (synplify)

On Friday, July 14, 2023 at 7:23:17 AM UTC-4, Richard Damon wrote:
> On 7/14/23 6:30 AM, KJ wrote: 
> > On Thursday, July 13, 2023 at 7:18:37 AM UTC-4, Stef wrote: 
> >> On 2023-07-11 Stef wrote in comp.arch.fpga: 
> >> 
> >> But the question remains valid: how to define multi-cycle constraints? 
> >> It is a bit absurd to require passing timing for a 200MHz clock when 
> >> some of these counters only run at a few kHz. 
> >> 
> > I haven't used Lattice tools, so I don't know the answer to your question. However, your complaint "...a bit absurd to require passing timing for a 200MHz clock when some of these counters only run at a few kHz" is very wrong. Every bit in a counter will depend on all of the lower/less significant bits. In other words, bits 7-1 will depend on bit 0. Bit 0 will be toggling at a 200 MHz rate so the logic for computing bit 7 will have to operate at that speed as well. 5 ns after the counter is at 11111111 all bits will be flipping to 00000000. To see these logic paths, just take a look at the post-fit logic and you'll see that what I described is correct. 
> > 
> > So the entire premise of your question is not correct. Even if you do find out how to add multi-cycle constraints in your tool, you'll want to be careful. The tools don't know that the constraint you entered is not correct which means it won't report a valid timing problem because of this error. You could end up scratching your head trying to figure out why things are acting flaky (i.e. an actual timing problem) when the tool says that the timing is correct. As far as I know, there is no 'error checking' to see that user supplied constraints are in fact correct. 
> > 
> > Kevin Jennings
> The OP said that it was a counter with enable, and the enable only 
> occured every N cycles, so your statement isn't true. 
> 
> The enable -> counter-ff needs to meet the requirement, but that signal 
> will tend to feed the last part of the logic, so shouldn't be a problem, 
> the timing limitation being the carry chain from a low bit to a high bit.

If the counter is running with an enable only 1 in N clock cycles, the carry chain has N clock cycles to propagate.  The only signal that needs to be timed at 1 clock cycle is the enable. 

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  Rick C.

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