Hi All, I'm synthesizing the IP core for my chip using the Altera Quartus tools. When I define constraints in the SDC file for the Timing Quest analyser & fitter, I use the derive_pll_clocks command to automatically generate clocks provided by the PLLs. However this command generates the clock with names like this: out_clk_pll:out_clk_pll_1|altpll:altpll_component|_clk0 (when used with -use_tan_name option) or: out_clk_pll_1|altpll_component|pll|clk[0] when used without this option. However, when my PLL is instantiated this way: out_clk_pll_1 : out_clk_pll port map ( areset => aclr, inclk0 => CLK40_1, c0 => out_clk80, c1 => out_clk80_latch, c2 => out_clk80_data, locked => open); I'd like to be able to generate clocks with the names like out_clk80, out_clk80_latch and so on... (i.e. with names of connected signals). Is there any way to achieve this behaviour? -- TIA & Regards, Wojtek
Symbolic names for pll derived clocks in SDC file? (quartus)
Started by ●June 7, 2007
Reply by ●June 8, 20072007-06-08
Wojtek, If you are using "derive_pll_clocks", there is no way to customize the generated clock name, so you only get the two choices. But you do not need to use "derive_pll_clocks". Instead, you can simply add your own create_generated_clock statements, and use the "- name" argument to name your clock exactly the way you want it. The best way to do this is to first call derive_pll_clocks, and then look for the messages that indicate exactly the generated clocks that were created. Then copy the commands into your golden SDC file and then simply modify the "-name" argument. You can also check the generated clocks from "report_sdc" or you can use "write_sdc" to generate a copy of the SDC with the generated clocks (but be careful to give write_sdc a different file name not to overwrite your golden SDC file). Obviously, this is a tradeoff between: 1) the convenience of TimeQuest generated PLL clocks for you and ensuring that you always get the right clock every time you change the PLL settings. But having to use the pre-defined clock name 2) the flexibility to name the clock your own way, but forcing you to have the discipline to change the SDC file every time you change the PLL settings We are considering adding a way to rename the clock, exactly to allow users to get the best of both worlds, but we currently do not have any release date for that. Hope this helps and that you are enjoying the benefits of TimeQuest. -David Karchmer TimeQuest team
Reply by ●June 8, 20072007-06-08
Wojtek, I forgot to say that if you are using Quartus II V7.1, TimeQuest will cross check the clocks defined in the SDC with the PLL settings, and will give warnings if it finds any differences. This in case you go with the explicit create_generated_clocks but you forget to edit the SDC after modifying the PLL settings. -David
Reply by ●June 8, 20072007-06-08
Thanks. What I need is to have the phase relationship automatically updated, whenever I change any settings in the PLL. Anyway my questions was probably stupid. It can be done just with the features of the Tcl: derive_pll_clocks set out_clk80 "out_clk_pll_1|altpll_component|pll|clk[0]" set out_clk80_latch "out_clk_pll_1|altpll_component|pll|clk[1]" set out_clk80_data "out_clk_pll_1|altpll_component|pll|clk[2]" then: set_output_delay -clock $out_clk80_latch -add_delay 1.0 [get_ports {IFIFO_OUT_DPRSNT}] set_output_delay -clock $out_clk80_latch -add_delay 1.0 [get_ports {IFIFO_OUT_CT[1]}] -- Thanks & Regards, Wojtek