I am an electronics student and pretty new in FPGAs' use.
I am interested in to send images to a monitor from the FPGA.
I have already performed a test using the Spartan 3 xilinx board based on
an example I found at the Internet and it worked perfectly. Now I am trying
to translate the same example to the ML405 xilinx board, however it doesn't
work correctly.
I wonder if someone could give me a hand to solve this problem. I add my
vhdl code and ucf file
lalo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
port(clk100_in : in std_logic;
red_out : out std_logic_vector(4 downto 0);
green_out : out std_logic_vector(4 downto 0);
blue_out : out std_logic_vector(4 downto 0);
hs_out : out std_logic;
vs_out : out std_logic);
end top;
architecture Behavioral of top is
signal clk25 : std_logic;
signal clk50 : std_logic;
signal hcounter : integer range 0 to 800;
signal vcounter : integer range 0 to 521;
signal color: std_logic_vector(2 downto 0);
begin
-- generate a 50Mhz clock
process (clk100_in)
begin
if clk100_in'event and clk100_in='1' then
clk50 <= not clk50;
end if;
end process;
-- generate a 55Mhz clock
process (clk50)
begin
if clk50'event and clk50='1' then
clk25 <= not clk25;
end if;
end process;
-- change color every one second
p1: process (clk25)
variable cnt: integer;
begin
if clk25'event and clk25='1' then
cnt := cnt + 1;
if cnt = 25000000 then
color <= color + "001";
cnt := 0;
end if;
end if;
end process;
p2: process (clk25, hcounter, vcounter)
variable x: integer range 0 to 639;
variable y: integer range 0 to 479;
begin
-- hcounter counts from 0 to 799
-- vcounter counts from 0 to 520
-- x coordinate: 0 - 639 (x = hcounter - 144, i.e., hcounter -Tpw-Tbp)
-- y coordinate: 0 - 479 (y = vcounter - 31, i.e., vcounter-Tpw-Tbp)
x := hcounter - 144;
y := vcounter - 31;
if clk25'event and clk25 = '1' then
-- To draw a pixel in (x0, y0), simply test if the ray trace to it
-- and set its color to any value between 1 to 7. The following example
simply sets
-- the whole display area to a single-color wash, which is changed every
one
-- second.
if x < 640 and y < 480 then
-- red_out <= "0000" & color(0);
-- green_out<= "0000" & color(1);
-- blue_out <= "0000" & color(2);
red_out <= "11111";
green_out<= "11111";
blue_out <= "11111";
else
-- if not traced, set it to "black" color
red_out <= "00000";
green_out<= "00000";
blue_out <= "00000";
end if;
-- Here is the timing for horizontal synchronization.
-- (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
-- Pulse width: Tpw = 96 cycles @ 25 MHz
-- Back porch: Tbp = 48 cycles
-- Display time: Tdisp = 640 cycles
-- Front porch: Tfp = 16 cycles
-- Sync pulse time (total cycles) Ts = 800 cycles
if hcounter > 0 and hcounter < 97 then
hs_out <= '0';
else
hs_out <= '1';
end if;
-- Here is the timing for vertical synchronization.
-- (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
-- Pulse width: Tpw = 1600 cycles (2 lines) @ 25 MHz
-- Back porch: Tbp = 23200 cycles (29 lines)
-- Display time: Tdisp = 38400 cycles (480 lines)
-- Front porch: Tfp = 8000 cycles (10 lines)
-- Sync pulse time (total cycles) Ts = 416800 cycles (521 lines)
if vcounter > 0 and vcounter < 3 then
vs_out <= '0';
else
vs_out <= '1';
end if;
-- horizontal counts from 0 to 799
hcounter <= hcounter+1;
if hcounter = 800 then
vcounter <= vcounter+1;
hcounter <= 0;
end if;
-- vertical counts from 0 to 519
if vcounter = 521 then
vcounter <= 0;
end if;
end if;
end process;
end behavioral;
Net "clk100_in" Loc = "AB14";
#------------------------------------------------------------------------------
# Viretex-4 VGA P2 Port:
#------------------------------------------------------------------------------
#RED
# LOC = R6; #VGA_R0
# LOC = R7; #VGA_R1
#NET red_out<0> LOC = P9; #VGA_R2
NET red_out<0> LOC = F3; #VGA_R3
NET red_out<1> LOC = H7; #VGA_R4
NET red_out<2> LOC = E3; #VGA_R5
NET red_out<3> LOC = G5; #VGA_R6
NET red_out<4> LOC = D3; #VGA_R7
# drive strength and speed for VGA
NET red_out<*> SLEW = FAST;
NET red_out<*> DRIVE = 8;
#GREEN
# LOC = N9; #VGA_G0
# LOC = N6; #VGA_G1
#NET green_out<0> LOC = P6; # VGA_G2
NET green_out<0> LOC = J3; # VGA_G3
NET green_out<1> LOC = K7; # VGA_G4
NET green_out<2> LOC = K3; # VGA_G5
NET green_out<3> LOC = G10; # VGA_G6
NET green_out<4> LOC = K6; # VGA_G7
# drive strength and speed for VGA
NET green_out<*> SLEW = FAST;
NET green_out<*> DRIVE = 8;
#BLUE
# LOC = P10; #VGA_B0
# LOC = P11; #VGA_B1
#NET blue_out<0> LOC = P8; # VGA_B2
NET blue_out<0> LOC = F4; # VGA_B3
NET blue_out<1> LOC = J4; # VGA_B4
NET blue_out<2> LOC = G9; # VGA_B5
NET blue_out<3> LOC = J5; # VGA_B6
NET blue_out<4> LOC = H3; # VGA_B7
# drive strength and speed for VGA
NET blue_out<*> SLEW = FAST;
NET blue_out<*> DRIVE = 8;
NET clk25 LOC = AC7; #VGA_CLK
NET clk25 IOSTANDARD = LVDCI_33;
NET clk25 SLEW = FAST;
NET clk25 DRIVE = 8;
NET hs_out LOC = C3; #HSYNC
NET hs_out SLEW = FAST;
NET hs_out DRIVE = 8;
NET vs_out LOC = D4; #VSYNC
NET vs_out SLEW = FAST;
NET vs_out DRIVE = 8;
vga in virtex 4
Started by ●November 28, 2009
Reply by ●November 28, 20092009-11-28
On Nov 28, 9:29=A0am, "lalop" <euar...@yahoo.com.mx> wrote:> I am an electronics student and pretty new in FPGAs' use. > > I am interested in to send images to a monitor from the FPGA. > I have already performed a test using the Spartan 3 xilinx board based on > an example I found at the Internet and it worked perfectly. Now I am tryi=ng> to translate the same example to the ML405 xilinx board, however it doesn='t> work correctly. > > I wonder if someone could give me a hand to solve this problem. I add my > vhdl code and ucf file > > lalo >[snip] lalo, In what way doesn't it work right? I assume you pretty much copied the code from the other project. You did check the pinout definitions in your .ucf file against the board documentation? Does the Virtex 4 board have the same hardware for VGA output (D/A Converter or just resistors) as the old board? Most video D/A Converters need a clock signal as well as synch and data. Your clocking is a bit of a mess. I imagine you may have inherited some of it from the prior project, but it's not generally good practice to make ripple counters in an FPGA. Your net clk25 in the .ucf doesn't correspond to a top module port. Is this supposed to drive the D/A converter clock? Regards, Gabor
Reply by ●November 23, 20152015-11-23
On Saturday, November 28, 2009 at 10:27:24 PM UTC+6, Gabor wrote:> On Nov 28, 9:29�am, "lalop" <euar...@yahoo.com.mx> wrote: > > I am an electronics student and pretty new in FPGAs' use. > > > > I am interested in to send images to a monitor from the FPGA. > > I have already performed a test using the Spartan 3 xilinx board based on > > an example I found at the Internet and it worked perfectly. Now I am trying > > to translate the same example to the ML405 xilinx board, however it doesn't > > work correctly. > > > > I wonder if someone could give me a hand to solve this problem. I add my > > vhdl code and ucf file > > > > lalo > > > [snip] > > lalo, > > In what way doesn't it work right? I assume you pretty much copied > the code from the other project. You did check the pinout definitions > in your .ucf file against the board documentation? > > Does the Virtex 4 board have the same hardware for VGA output > (D/A Converter or just resistors) as the old board? Most video > D/A Converters need a clock signal as well as synch and data. > > Your clocking is a bit of a mess. I imagine you may have > inherited some of it from the prior project, but it's not > generally good practice to make ripple counters in an FPGA. > > Your net clk25 in the .ucf doesn't correspond to a top > module port. Is this supposed to drive the D/A converter > clock? > > Regards, > GaborGabor, lalo I meet similar problem, and gave clk to adv7125, as I mentioned in my post https://groups.google.com/forum/#!topicsearchin/comp.arch.fpga/vga/comp.arch.fpga/l8t2fDa2TVE lalo did you get some success or not ? but there are no any result yet.
