Verilog Styles for Synthesis of Digital Systems
This book is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to those just entering the field. The text uses a simpler language (Verilog) and standardizes the methodology to the point where even novices can get medium complex designs through to gate-level simulation in a short period of time. Requires a working knowledge of computer organization, Unix, and X windows. Some knowledge of a programming language such as C or Java is desirable, but not necessary. Features a large number of worked examples and problems--from 100 to 100k gate equivalents--all synthesized and successfully verified by simulation at gate level using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx. Basic Language Constructs. Structural and Behavioral Specification. Simulation. Procedural Specification. Design Approaches for Single Modules. Validation of Single Modules. Finite State Machine Styles. Control-Point Writing Style. Managing Complexity--Large Designs. Improving Timing, Area, and Power. Design Compiler. Synthesis to Standard Cells. Synthesis to FPGA. Gate Level Simulation and Testing. Alternative Writing Styles. Mixed Technology Design. For anyone wanting an accessible, accelerated introduction to the cutting-edge tools for Digital Hardware Design.
Why Read This Book
You will learn pragmatic, synthesizable Verilog coding styles and patterns that reduce surprises when you move RTL into synthesis and gate-level simulation. The book emphasizes hands-on examples and synthesis-proven idioms so you can produce cleaner, tool-friendly RTL faster.
Who Will Benefit
FPGA and RTL engineers (junior-to-mid level) who need to write robust, synthesizable Verilog and understand how synthesis tools translate RTL to gates.
Level: Intermediate — Prerequisites: Basic digital logic and computer organization; familiarity with programming (C/Java helpful) and some exposure to Verilog syntax or other HDLs. Unix/X-Windows experience helps for running typical EDA tools.
Key Takeaways
- Write synthesizable Verilog idioms for combinational and sequential logic that map reliably to gates.
- Design and implement finite-state machines and datapaths using tool-friendly RTL styles.
- Avoid common non-synthesizable constructs and coding patterns that break synthesis or timing.
- Interpret synthesis reports and simulation results to iterate toward gate-level-correct designs.
- Apply practical synthesis flows and use examples of real designs (small to mid-scale) to validate RTL.
Topics Covered
- Introduction: synthesis goals and methodology
- Verilog review: synthesizable subsets and modeling styles
- Combinational logic: coding patterns and hazards
- Sequential logic: registers, resets, and clock domains
- Finite-state machines: style, encoding, and synthesis pitfalls
- Datapath construction: operators, buses, and arithmetic
- Memories and inference: RAM/ROM styles and block RAM mapping
- Hierarchical design and module interfacing
- Testbench strategies and gate-level verification
- Synthesis toolflows: translating RTL to gates and common options
- Case studies: examples from 100 to 100k gate equivalents
- Appendices: coding checklists and synthesis tips
Languages, Platforms & Tools
How It Compares
More focused on practical, synthesis-proven RTL styles than Palnitkar's Verilog HDL (which is a broader language reference); complements FPGA prototyping books that concentrate on board-level implementation by emphasizing clean, synthesizable RTL.
