BGA and QFP at Home 1 - A Practical Guide.

Victor Yurkovsky October 13, 20132 comments

It is almost universally accepted by the hobbyists that you can't work with high-density packages at home.  That is entirely incorrect.  I've been assembling and reflowing BGA circuit boards at home for a few years now.  BGAs and 0.5mm-pitch QFPs are well within the realm of a determined amateur. 

This series of articles presents practical information on designing and assembling boards with high-density packages at home.  While the focus is on FPGA packages, most of...


Learning VHDL - Basics

Enrico Garante June 15, 20135 comments

Since FPGA are becoming more accessible to the hobbyist, learning how to use them can be really useful for certain applications, like DSP and video generation; moreover, engineers that are able to code in VHDL/Verilog are always requested on the job market.

In this tutorial I will cover the basics of Xilinx ISE and VHDL. I willl base my code on the Basys2 board from Digilent: it is really cheap (especially for students) and has a lot of features on board, as you can see from the picture...


VGA Output in 7 Slices. Really.

Victor Yurkovsky September 25, 20121 comment

Ridiculous? Read on - I will show you how to generate VGA timing in seven XilinxR Spartan3R slices.Some time ago I needed to output video to a VGA monitor for my Apple ][ FPGA clone.  Obviously (I thought), VGA's been done before and all I had to do was find some Verilog code and drop it into my design.  As is often the case (with me anyway), the task proved to be very different from my imagined 'couple of hours to integrate the IP'.I found some example code for my board.  I...


MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)

Christopher Felton September 13, 201210 comments
Introduction

To demonstrate the echo on an FPGA board an interface to an audio ADC/DAC chip will be used. The following will explain the connection to the audio codec and the HDL module used to interface.

Audio Codec Interface

I have two boards with TI AIC23b audio codecs. The AIC23 has a configuration interface (ability to program the registers) and a streaming audio interface. The SPI mode will be used to configure the codec and the I2S interface is used to send and...


How to start in FPGA development? - Some tips

Nuria Orduna August 30, 20123 comments
Introduction

The aim of this tutorial is to show some useful tips for people like me that one day started from zero to work with FPGA's. Why FPGA's? Because they are easy to use and they are not too expensive, and they are usually used in lab courses to let students "play" with them.

1: How to choose the right FPGA?

As you may know there are a lot of different FPGA's, brands and models. How to choose the right one? It's very difficult to say that before knowing which will be the...


MyHDL FPGA Tutorial II (Audio Echo)

Christopher Felton July 18, 2012
Introduction

This tutorial will walk through an audio echo that can be implemented on an FPGA development board.  This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial.  This project will require an FPGA board with an audio codec and the interface logic to the audio codec.

Review the Previous Tutorial

The previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board.  In that tutorial we introduced the basics of a MyHDL module....


Designing a FPGA Micro Pt2 - Clock and Counter build and test.

Paul J Clarke June 26, 20121 comment

So last time I looked and talked about designing my own PIC12F509. I concluded by talking shortly about the clock that is used inside the chip. If you have not read this it may be a good time to jump back and read what I have written so far. I’ll be putting links back at the top of every blog from now on to help.State Machine ‘v’ Micro in a FPGADesigning a FPGA Micro Pt1 - Start The ClockOk so this last week I started writing the VHDL code for my PIC core that I’ll be...


Using GHDL for interactive simulation under Linux

Martin Strubel October 24, 2011

The opensource and free VHDL simulator 'GHDL' has been out for many years, but like many other opensource tools, it has caught limited attention from the industry. I can hear you thinking: 'If it doesn't cost money, it can't be worth it'. Well, I hope this short overview will change your mind and even whet your appetite for more. Because, using some extensions, you can do some quite funky stuff with it that will save you a lot of debugging work. For example, simulate your real world software...


Developing FPGA-DSP IP with Python

Christopher Felton March 16, 20101 comment

This blog post was previously titled MyHDL ASIC Proven (How is this related to FPGAs?) but the blog post has been updated and mainly discusses developing FPGA-DSP IP with Python / MyHDL. The original content is still present but the post has been reorganized and expanded. Original post 16-Mar-2010.

Developing FPGA-DSP IP with Python / MyHDL

Using Python to develop DSP logic for an FPGA is very powerful. The Python ecosystem contains many packages including numerical and...


BGA and QFP at Home 1 - A Practical Guide.

Victor Yurkovsky October 13, 20132 comments

It is almost universally accepted by the hobbyists that you can't work with high-density packages at home.  That is entirely incorrect.  I've been assembling and reflowing BGA circuit boards at home for a few years now.  BGAs and 0.5mm-pitch QFPs are well within the realm of a determined amateur. 

This series of articles presents practical information on designing and assembling boards with high-density packages at home.  While the focus is on FPGA packages, most of...


Using GHDL for interactive simulation under Linux

Martin Strubel October 24, 2011

The opensource and free VHDL simulator 'GHDL' has been out for many years, but like many other opensource tools, it has caught limited attention from the industry. I can hear you thinking: 'If it doesn't cost money, it can't be worth it'. Well, I hope this short overview will change your mind and even whet your appetite for more. Because, using some extensions, you can do some quite funky stuff with it that will save you a lot of debugging work. For example, simulate your real world software...


Developing FPGA-DSP IP with Python

Christopher Felton March 16, 20101 comment

This blog post was previously titled MyHDL ASIC Proven (How is this related to FPGAs?) but the blog post has been updated and mainly discusses developing FPGA-DSP IP with Python / MyHDL. The original content is still present but the post has been reorganized and expanded. Original post 16-Mar-2010.

Developing FPGA-DSP IP with Python / MyHDL

Using Python to develop DSP logic for an FPGA is very powerful. The Python ecosystem contains many packages including numerical and...


MyHDL FPGA Tutorial II (Audio Echo)

Christopher Felton July 18, 2012
Introduction

This tutorial will walk through an audio echo that can be implemented on an FPGA development board.  This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial.  This project will require an FPGA board with an audio codec and the interface logic to the audio codec.

Review the Previous Tutorial

The previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board.  In that tutorial we introduced the basics of a MyHDL module....


VGA Output in 7 Slices. Really.

Victor Yurkovsky September 25, 20121 comment

Ridiculous? Read on - I will show you how to generate VGA timing in seven XilinxR Spartan3R slices.Some time ago I needed to output video to a VGA monitor for my Apple ][ FPGA clone.  Obviously (I thought), VGA's been done before and all I had to do was find some Verilog code and drop it into my design.  As is often the case (with me anyway), the task proved to be very different from my imagined 'couple of hours to integrate the IP'.I found some example code for my board.  I...


How to start in FPGA development? - Some tips

Nuria Orduna August 30, 20123 comments
Introduction

The aim of this tutorial is to show some useful tips for people like me that one day started from zero to work with FPGA's. Why FPGA's? Because they are easy to use and they are not too expensive, and they are usually used in lab courses to let students "play" with them.

1: How to choose the right FPGA?

As you may know there are a lot of different FPGA's, brands and models. How to choose the right one? It's very difficult to say that before knowing which will be the...


Learning VHDL - Basics

Enrico Garante June 15, 20135 comments

Since FPGA are becoming more accessible to the hobbyist, learning how to use them can be really useful for certain applications, like DSP and video generation; moreover, engineers that are able to code in VHDL/Verilog are always requested on the job market.

In this tutorial I will cover the basics of Xilinx ISE and VHDL. I willl base my code on the Basys2 board from Digilent: it is really cheap (especially for students) and has a lot of features on board, as you can see from the picture...


MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)

Christopher Felton September 13, 201210 comments
Introduction

To demonstrate the echo on an FPGA board an interface to an audio ADC/DAC chip will be used. The following will explain the connection to the audio codec and the HDL module used to interface.

Audio Codec Interface

I have two boards with TI AIC23b audio codecs. The AIC23 has a configuration interface (ability to program the registers) and a streaming audio interface. The SPI mode will be used to configure the codec and the I2S interface is used to send and...


Designing a FPGA Micro Pt2 - Clock and Counter build and test.

Paul J Clarke June 26, 20121 comment

So last time I looked and talked about designing my own PIC12F509. I concluded by talking shortly about the clock that is used inside the chip. If you have not read this it may be a good time to jump back and read what I have written so far. I’ll be putting links back at the top of every blog from now on to help.State Machine ‘v’ Micro in a FPGADesigning a FPGA Micro Pt1 - Start The ClockOk so this last week I started writing the VHDL code for my PIC core that I’ll be...