Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 2 years ago10 replieslatest reply 3 months ago772 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Lattice: Utilization and Clock Report

Started by cubosubtil 3 weeks ago3 replieslatest reply 1 week ago16 views
Hello,I have only one clock in my design and the number of clock load in my clock report(.par) does not correspond to the number of the registers in the map report(.mrp),...

simple line drive generator doesn't work properly

Started by ombz 2 weeks ago3 replieslatest reply 1 week ago22 views
Hi guysI don't have any real-world experience with synthesizable VHDL and FPGA's but I've been really curious about it for a long time. So I've found an old experimenter's...

Synchronizing clock cycles of FPGA in Mojo V3 with the clock cycle of a signal generator

Started by embeddedelectronics 1 month ago4 replieslatest reply 4 weeks ago60 views
Hi, So I want to synchronize the clock cycle of an FPGA in mojo V3 development board, whose default clock cycle is 50 MHz with a function generator. Currently,...


Started by maha_66 1 month ago3 replieslatest reply 1 month ago38 views
Hello! I am currently working on a matrix multiplication project. After performing the multiplication of the matrices, I am trying to build a module that can write...

VHDL Matrix Multiplication using UART and BRAM

Started by maha_66 2 months ago2 replieslatest reply 2 months ago52 views
My project involves performing matrix multiplication in vhdl. The two input matrices (8 bits each) are sent using a terminal and received via UART Rx. The FPGA...

Implementing octave algorithm in FPGA using c++

Started by Abhinav90 2 months ago11 replieslatest reply 2 months ago171 views
I am currently working on writing a scrambler and DeScrambler code for Orthogonal Frequency Division Multiplexing(OFDM). I am planning to write an algorithm for...

Searching for info about very old FPGA devices

Started by rodrigomelo9 3 months ago3 replieslatest reply 3 months ago54 views
Hello. My name is Rodrigo and I am from Argentina. I was looking for very old datasheets without success :-( (I searched a lot in google,, alldatasheets,...

HDL to Schematic Reporting

Started by Sanram 3 months ago5 replieslatest reply 3 months ago53 views
I am looking at a tool (or combination of tools) to perform the following. Please advise.1) Read Verilog/VHDL RTL input code and convert it to technology independent...

Mux versus internal high impledance

Started by prashantpd 3 months ago5 replieslatest reply 3 months ago46 views
Hi, I have been an FPGA designer for more than a decade now and tutor a class on FPGA design at University presently. In all these years, I have had two ways of...

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