It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Humor helps us take back control and to connect - two things we have lost in our fight against the pandemic. Feel free to share your best finds. they're...

How about we share with each others the impact that the current pandemic is having on our lives & work?  I will start. First, I am located in Canada, where...

Hi,I can't seem to find a QSPI slave IP core. Any pointers? My application needs to interface with a QSPI master interface on a processor.Thanks

I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box on the HDMI...

Hi All, I am starting to learn Verilog in order to program FPGAs. I have a project where I need to take three digital signals coming from three hall sensors on...

Hello,by now, I suspect that most of you are already signed-up for the upcoming Embedded Online Conference that I am currently organizing with Jacob Beningo (@beningjw).I...

Hi,I am an FPGA engineer in charge of developing a test application that must offload a continuous test data stream between host PC and a test hardware. I do not...

Together with my friend Jacob Beningo, we have been working hard lately on putting together a platform to hold online conferences:https://www.embeddedonlineconference.comBefore...

Hello,I implemented running sum filter In FPGA.  Input width(IW) is 8 and the log(based two) of the maximum number of averages(LGMEM) is 14. The output/accumulator...