Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 1 year ago7 replieslatest reply 4 months ago618 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Is this an FPGA job spec or a lecture on FPGA?

Started by kaz 2 days ago26 views
A current active contract role for an FPGA engineer  is around but sounds very strange in that it tries to explain the FPGA more than the required skills for the...

FPGA perspective of pins versus PCB perspective

Started by kaz 6 days ago2 replieslatest reply 6 days ago18 views
Hi All,I am looking for any hints on  FPGA pin constraints and their PCB perspective.Are there any established rules for both designers (FPGA & PCB) to work...

Ideas for simple bitrate regulation

Started by Kamilpl 3 weeks ago5 replieslatest reply 3 weeks ago89 views
Hello everyone,I would like to implement a bitrate regulation on an fpga board.Clock + data are incoming at bitrate with a +/- percentage. Then after a channel coder...

If FPGAs didn't work we won't be here?

Started by kaz 2 months ago2 replieslatest reply 2 months ago60 views
Being over-careful  is good practice especially for presentation to the management but factual issues should not be distorted for that sake.What I mean if an FPGA...

Greatest Conferences?

Started by stephaneb 3 months ago5 replieslatest reply 2 months ago308 views
I have been juggling with the idea to organize a DSP+Embedded+FPGA conference for a while now.  But I won't do it until I feel I can organize an event where everyone...

When (and why) is it a good idea to use an FPGA in your embedded system design?

Started by stephaneb 2 months ago11 replieslatest reply 2 months ago2342 views
Once we are done with this thread, the vision is for readers to get a basic understanding of when should an FPGA be considered in the design of an Embedded System...

IIR in FPGA

Started by DK999 4 months ago11 replieslatest reply 2 months ago153 views
Hi guys!So far I've made two versions of the IIR, one is more async (IIR_Biquad_II.vhd) and one uses a state machine (IIR State). The more async one was derived...

Timing constraints priority

Started by kaz 3 months ago1 replylatest reply 3 months ago35 views
Hi All,I am trying to understand an issue with synopsis timing constraints priority (TimeQuest in fact). Suppose I set clock group command to say clk1 is unrelated...

Got syntax errors in both mainboard and uart-receiver files

Started by Jamanen 3 months ago2 replieslatest reply 3 months ago21 views
I want to design a UART receiver/transmitter and by now I already developed the receiver vhdl file but when declare and instantiate the the receiver component on...

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