Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 3 years ago10 replieslatest reply 6 months ago1229 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Running Sum filter

Started by Adira 4 days ago12 replieslatest reply 4 hours ago129 views
Hello,I implemented running sum filter In FPGA.  Input width(IW) is 8 and the log(based two) of the maximum number of averages(LGMEM) is 14. The output/accumulator...

Expect Downtime

Started by stephaneb 5 days ago14 replieslatest reply 5 hours ago141 views
Edit #1 01/19 10:12am: well, false start with the new host.  Their migration team was supposed to help me through the process this morning but I am not hearing...

New Embedded Online Conference website, need your help testing it.

Started by stephaneb 2 days ago14 replieslatest reply 1 day ago115 views
Together with my friend Jacob Beningo, we have been working hard lately on putting together a platform to hold online conferences:https://www.embeddedonlineconference.comBefore...

Back online - Migration done

Started by stephaneb 4 days ago1 replylatest reply 4 days ago84 views
It looks like the migration went well.  I found a couple of errors but solved them quickly.  I will continue to do some testing to make sure that everything is...
I am trying to bring up the DE10 Nano kit that has Cyclone V FPGA using the open source Cascade compiler from VMware. It uses Quartus...

timing analysis query

Started by dayana42200 2 weeks ago23 views
Hello everyone.Currently, Im designing a processing element.This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.I have problem...

LVDS as a comparator

Started by Tanu3 2 weeks ago19 views
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal...

VHDL : function not recognizing a type defined in package

Started by jmca 3 weeks ago1 replylatest reply 2 weeks ago22 views
Hi,I am trying to write a function that reads from csv file and formats data to fixed point so it can be used to initialize ROM contents.The function is contained...

UDP or TCP/IP FPGA solution for max streaming rate of 640 Mbps

Started by jmca 1 month ago5 replieslatest reply 3 weeks ago44 views
Hi,I am an FPGA engineer in charge of developing a test application that must offload a continuous test data stream between host PC and a test hardware. I do not...

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