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Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 3 years ago10 replieslatest reply 4 weeks ago1077 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Tips for using Xilinx Ultra RAMs

Started by weetabixharry 5 days ago2 replieslatest reply 3 days ago22 views
What are the main considerations that I should be aware of if I want to use Ultra RAMs in my design?I am familiar with the Block RAMs used in 5-, 6- and 7-series...

recovery/removal violations, does it always matter?

Started by kaz 2 weeks ago9 replieslatest reply 4 days ago26 views
Hi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...

FPGA output pulsating in real time

Started by abdul_samad 1 week ago1 replylatest reply 1 week ago19 views
Hi,I am working on a digital down conversion module for a project of mine. The module down converts a  signal at IF 455 KHz received through an ADC, multiplies...

Fixed Point Library for Python

Started by smlgit 2 weeks ago7 replieslatest reply 2 weeks ago127 views
Hi everyone,As part of a large FPGA/DSP project, I built a c extension library for python that mimicks the vhdl standard library fixed point functionality (https://github.com/smlgit/fpbinary)....

register clear on read

Started by kamalovich 2 weeks ago4 replieslatest reply 2 weeks ago27 views
hi all !I am doing a BER (BIT ERROR RATE) in vhdl and I have to put 2 registers clear on read which counts the number of words in error and the number of bits...

Spammers are getting more sophisticated

Started by stephaneb 1 month ago4 replieslatest reply 1 month ago222 views
Just a quick post to inform you of a scheme used by spammers lately on the Related sites.Here's the scheme:They create an account on one of the Related sites and...

metastabilty with multicycle

Started by nori 1 month ago3 replieslatest reply 1 month ago33 views
Hi All,This thought occurred to me regarding multicycle path.Assume I set multicycle of 2. Then this implies that data delay from launch edge(0) will respect the...

fpga spartan 6 io ports are no longer working

Started by ahmed1600 2 months ago2 replieslatest reply 2 months ago23 views
HELLO there,i have spartan 6 of the familyxlc9  but i am facing a severe problem with it . first i can burn successfully with jtag on it .its power is okay but...

Live Streaming #3

Started by stephaneb 2 months ago9 replieslatest reply 2 months ago88 views
Today's live streaming will be short - one quick draw and then testing of the split screen.

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