Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 8 months ago4 replieslatest reply 6 months ago365 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Effective schematic for GPIO pin

Started by l8rPIC 1 month ago1 replylatest reply 1 month ago36 views
I am working on a project using the cyclone V from Altera. The FPGA has 3.3v GPIO pins and I would like to know what I could use to mimic a GPIO pins output. I am...

Overloading assignment operator '<=' in vhdl

Started by LabPe43 1 month ago1 replylatest reply 1 month ago37 views
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DSP Filter Verification in FPGA

Started by srid 2 months ago30 replieslatest reply 2 months ago131 views
I am designing the FIR filter for up conversion in FPGA. Input to the FIR filter is 16 bits wide (-32768 to 32767) with the maximum co-eff value of 32767. This produces...

Programmable SoC and SoC FPGA

Started by jbmore 2 months ago5 replieslatest reply 2 months ago50 views
Hello, What's the difference between Programmable SoC and SoC FPGA ?  Thank you

FPGA and VHDL Language for beginner

Started by hey_gluppy 2 months ago3 replieslatest reply 2 months ago36 views
Hi, my name is IMA and I am now studying about the FPGA VHDL language to generate the gate signal for my converter circuit. I have basic C++ programming...

Synplify Pro for Lattice not working

Started by CraigMeyers 2 months ago4 replieslatest reply 2 months ago30 views
I put in a support ticket with Lattice. Nothing they suggested I try worked. Except installing on another Windows box. When I did not get the error on the other...

New Email Notifications System

Started by stephaneb 1 year ago5 replieslatest reply 3 months ago156 views
If I implemented the new email notification system well, this new thread should trigger an email notification to all members who have been approved to participate...

Guidelines for porting ASIC RTL to FPGA

Started by LabPe43 3 months ago3 replieslatest reply 3 months ago59 views
I wonder what are the guidelines for porting ASIC RTL to FPGA for emulation.1. Memory blocks need be adjusted for FPGA device specific features.2. DSP Elements...

DDC in FPGA with high speed ADC

Started by LoganathanN 3 months ago14 replieslatest reply 3 months ago150 views
Hi allI'm going to work with high speed ADC in my upcoming project. I'm having 4 ADC channels with 3.2GHz sampling rate interfaced with FPGA. I'm getting 40 samples...

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