Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 2 years ago10 replieslatest reply 5 months ago839 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Learning FPGA

Started by stephaneb 1 month ago16 replieslatest reply 2 weeks ago946 views
A few months ago, this community tackled the first FPGA FAQ titled When (and why) is it a good idea to use an FPGA in your embedded system design?.  Your contributions...

Activating CH7301 on SP605 board #xilinx #vhdl

Started by ajellis 4 weeks ago2 replieslatest reply 3 weeks ago23 views
HelloI am working on a project using the SP605 for a video application. Currently I'm trying to output a picture via the DVI output which is driven by a CH7301...

remains a black box sine it has not binding entity

Started by ajellis 2 months ago7 replieslatest reply 2 months ago55 views
HI I'm working on a design where I have implemented an I2C module which I'm trying to use as a component in another piece of VHDL. The problem I've got is that...

A Law compression for FPGA

Started by kaz 2 months ago7 replieslatest reply 2 months ago42 views
Hi all,Referring to this doc on A law compression (table 1): table is meant for 13 bits signed to 8 bits...

Lattice: Utilization and Clock Report

Started by cubosubtil 3 months ago3 replieslatest reply 2 months ago24 views
Hello,I have only one clock in my design and the number of clock load in my clock report(.par) does not correspond to the number of the registers in the map report(.mrp),...

simple line drive generator doesn't work properly

Started by ombz 2 months ago3 replieslatest reply 2 months ago26 views
Hi guysI don't have any real-world experience with synthesizable VHDL and FPGA's but I've been really curious about it for a long time. So I've found an old experimenter's...

Synchronizing clock cycles of FPGA in Mojo V3 with the clock cycle of a signal generator

Started by embeddedelectronics 3 months ago4 replieslatest reply 3 months ago77 views
Hi, So I want to synchronize the clock cycle of an FPGA in mojo V3 development board, whose default clock cycle is 50 MHz with a function generator. Currently,...


Started by maha_66 3 months ago3 replieslatest reply 3 months ago48 views
Hello! I am currently working on a matrix multiplication project. After performing the multiplication of the matrices, I am trying to build a module that can write...

VHDL Matrix Multiplication using UART and BRAM

Started by maha_66 4 months ago2 replieslatest reply 4 months ago83 views
My project involves performing matrix multiplication in vhdl. The two input matrices (8 bits each) are sent using a terminal and received via UART Rx. The FPGA...

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