Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 6 months ago4 replieslatest reply 4 months ago307 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

New Email Notifications System

Started by stephaneb 1 year ago5 replieslatest reply 1 week ago150 views
If I implemented the new email notification system well, this new thread should trigger an email notification to all members who have been approved to participate...

Guidelines for porting ASIC RTL to FPGA

Started by LabPe43 3 weeks ago3 replieslatest reply 2 weeks ago28 views
I wonder what are the guidelines for porting ASIC RTL to FPGA for emulation.1. Memory blocks need be adjusted for FPGA device specific features.2. DSP Elements...

DDC in FPGA with high speed ADC

Started by LoganathanN 2 weeks ago14 replieslatest reply 2 weeks ago115 views
Hi allI'm going to work with high speed ADC in my upcoming project. I'm having 4 ADC channels with 3.2GHz sampling rate interfaced with FPGA. I'm getting 40 samples...

Embedded World Videos Now Online

Started by stephaneb 2 weeks ago83 views
Maybe you've seen my latest blog post?  Producing these videos has...

Goldschmidt division algorithm

Started by kevin998x 3 weeks ago30 views
what is line 19 of trying to do ? it seems to me that it is transformed into 2-complement, but...

Synchronizing Multiple FPGA Prototype Boards

Started by qbitrex 2 months ago8 replieslatest reply 2 months ago61 views
My project requires large numbers of IO lines.I love the dedicated ATmega32U4 processor for serial comms on the Mojo, it...

PCB simulation and layout

Started by ombz 2 months ago13 replieslatest reply 2 months ago93 views
Dear all, This is probably an always re-occurring topic within electronics forums and one that probably leads to plenty of subjective inputs and hence: discussion....

sampling 800mbps data in virtex 5QV

Started by nilendra 2 months ago9 replieslatest reply 2 months ago45 views
We are trying for a space radar application. For that from ADC need to receive data at around 760MHz.Is it possible to achieve using rocketio ?

Packaging custom IP (master) in XPS

Started by vijji148 2 months ago1 replylatest reply 2 months ago23 views
Hi, I need to package a customized master IP with a set of hdl files, using XPS tool. As I am using Spartan 6 FPGA, I cannot use Vivado. Can anyone guide in doing...

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