It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Hello everyone!I am trying to implement Raised-cosine filter in VHDL. In the current simulation I am using the standard method of the filter simulation:- create...

Hi all,I am usig an AD9914 DDShttps://www.analog.com/media/en/technical-documentation/data-sheets/AD9914.pdfwith its DROVER output connected to a I/O of the FPGA...

Hello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...

Hello there,I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here: PS:I'd...

Hello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...

Hello, I am currently studying the implementation of a Polyphase Filter Bank channelizer designed by Xilinx in its XAPP1161. The architecture is composed by a single...

Hello,I'm new to UART for FPGA and recently I tried a demo project that I found at: https://www.fpga4fun.com/SerialInterface.htmlMy problem is using RxD_data_ready...

I've been working on a video streaming project using a zedboard and the ov7670 camera. My project is based on this one (capture and vga .vhd files): https://www.hackster.io/dhq/fpga-camera-system-14d6ea...

I have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to implement the...