It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Hi, I know nothing about FPGA, integrated circuits, electronics, et cetera. I do know that it's a field my father is interested in. A little background, he's worked...

I was given a DueProLogic(DPL) board last year as a birthday gift. I never could get it to work. After having built my desktop and having installed Quartus and the...

Recently I came into the possession of a ML310 (Virtex-II Pro) board made by Xilinx. IT is an old board and unfortunately, except for a few User Guides nothing can...

Due to lack of support from lattice - and also mi lack of experiece with Lattice: I come from the xlinx world - I am here to get help about integrating this IP on...

Hi All,I 've come across this case (please see figure below) .I have a synchronous system but four constants (A,B,C,D) are implemented on wires and any one of them...

How to use non-dedicated IO pins as clock source to FPGA PLL or Clock MUX?I try to use "PROHIBIT PRIMARY" preference, as described in:TN1263 ECP5 and ECP5-5G sysCLOCK...

Hi , I am working in Embedded Development Kit EDK 13.2 Virtex 5, on spi (one master one slave). Microblaze is operated at 50Mhz input clock. spi in edk is configured...

Hi.I'm trying to use FT601Q with FPGA. But I have some loss of data. And I don't know if this is an error in my FPGA code, or an error in FT601Q chip. FT601Q have...

I have a pretty simple verilog project, in Lattice Diamond 3.11.My top module instantiates an OSCH (Lattice IP library) oscillator at 133 mhz, and a 'ws2812b' module...