It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Hello,I implemented running sum filter In FPGA.  Input width(IW) is 8 and the log(based two) of the maximum number of averages(LGMEM) is 14. The output/accumulator...

Edit #1 01/19 10:12am: well, false start with the new host.  Their migration team was supposed to help me through the process this morning but I am not hearing...

Together with my friend Jacob Beningo, we have been working hard lately on putting together a platform to hold online conferences:https://www.embeddedonlineconference.comBefore...

It looks like the migration went well.  I found a couple of errors but solved them quickly.  I will continue to do some testing to make sure that everything is...

I am trying to bring up the DE10 Nano kit that has Cyclone V FPGA using the open source Cascade compiler https://github.com/vmware/cascade from VMware. It uses Quartus...

Hello everyone.Currently, Im designing a processing element.This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.I have problem...

I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal...

Hi,I am trying to write a function that reads from csv file and formats data to fixed point so it can be used to initialize ROM contents.The function is contained...

Hi,I am an FPGA engineer in charge of developing a test application that must offload a continuous test data stream between host PC and a test hardware. I do not...