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Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 4 years ago10 replieslatest reply 6 months ago1434 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Will this FPGA be suitable for DSP purposes?

Started by corn1996 2 days ago4 replieslatest reply 24 hours ago117 views
Hey guys! My masters degree thesis is digital lock-in amplifier. I want to make it on an FPGA to learn this piece of hardware. Basically I have a budget of 220€...

Quartus Prime Licensing

Started by Echoonezero 2 days ago1 replylatest reply 1 day ago20 views
Hello,I have the following questions:1. A Quartus Prime Lite version is sufficient for my FPGA design. Can I use only the Lite version in my company for commercial...

Libero SmartFusion 2 Pinout Chart

Started by cwible 2 months ago20 views
Hi everyone, I am trying to learn how to use the SmartFusion 2 Maker Kit for a research project. Right now I am trying to simply flash an LED but I cant find which...

Clock domain crossing

Started by vpsampath 2 months ago34 views
Constraints are essential when developing a new design. The constraints set up are the environmental, clock, test and power boundaries the designers must keep themselves...

Creating custom IP for zedboard

Started by shlomishab 2 months ago22 views
Hi all,I'm working on a video streming project with a zedboard and an ov7670 camera module. I found a similar project online, made by Mike Field, and I was able...

TinyFPGA BX Creating Two OR Gates

Started by Joe3502 6 months ago1 replylatest reply 2 months ago30 views
Hi all,  First off, I hope that you and your families are staying safe and well during this time of global pandemic.  I just received my TinyFPGA in the mail yesterday...
Hello everyone,I am migrating an old MAXPLUS II design to Quartus II. I could transfer the schematic files and the design is ready, but not able to migrate the...

Processing Gain at output of ADC

Started by rathnakarreddy 4 months ago2 replieslatest reply 4 months ago43 views
With adequate filtering after AD conversion, the SNR is calculated as,SNR=6.02*N+1.76+10*log(fs/(2*BW));N-> No: of ADC bitsThe term 10log(fs/2*BW) is referred...

How to avoid Blocking Statement in Verilog

Started by rathnakarreddy 4 months ago1 replylatest reply 4 months ago47 views
Hi,I have a matlab code and I have to convert it to verilog.The matlab code is as follows:/****************************************************************/clc;clear...

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