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Forums Update, Tips and Tricks - Please Read!
Started by 3 years ago●10 replies●latest reply 4 weeks ago●1077 viewsIt's been a few months since the launch of the new forums. Here are a few thoughts.
The thumbsup and beer buttons
If there is one thing that could have a...
Started by What are the main considerations that I should be aware of if I want to use Ultra RAMs in my design?I am familiar with the Block RAMs used in 5-, 6- and 7-series...
recovery/removal violations, does it always matter?
Started by 2 weeks ago●9 replies●latest reply 4 days ago●26 viewsHi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...
Hi,I am working on a digital down conversion module for a project of mine. The module down converts a signal at IF 455 KHz received through an ADC, multiplies...
Hi everyone,As part of a large FPGA/DSP project, I built a c extension library for python that mimicks the vhdl standard library fixed point functionality (https://github.com/smlgit/fpbinary)....
hi all !I am doing a BER (BIT ERROR RATE) in vhdl and I have to put 2 registers
clear on read which counts the number of words in error and the number
of bits...
Spammers are getting more sophisticated
Started by 1 month ago●4 replies●latest reply 1 month ago●222 viewsJust a quick post to inform you of a scheme used by spammers lately on the Related sites.Here's the scheme:They create an account on one of the Related sites and...
Hi All,This thought occurred to me regarding multicycle path.Assume I set multicycle of 2. Then this implies that data delay from launch edge(0) will respect the...
fpga spartan 6 io ports are no longer working
Started by 2 months ago●2 replies●latest reply 2 months ago●23 viewsHELLO there,i have spartan 6 of the familyxlc9 but i am facing a severe problem with it . first i can burn successfully with jtag on it .its power is okay but...
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