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Forums Update, Tips and Tricks - Please Read!
Started by 7 years ago●14 replies●latest reply 1 month ago●2490 viewsIt's been a few months since the launch of the new forums. Here are a few thoughts.
The thumbsup and beer buttons
If there is one thing that could have a...
Hi All, I am starting to learn Verilog in order to program FPGAs. I have a project where I need to take three digital signals coming from three hall sensors on...
LZW or BWC Compression cores for FPGAs
Started by 7 months ago●1 reply●latest reply 1 month ago●46 viewsHello,Can anyone recommend RTL level cores for LZW or BWC compression/decompresison engines? Thank you.Best regards,Sanjay
Implementing a folded FIR on FPGA
Started by 3 years ago●5 replies●latest reply 7 months ago●119 viewsHello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...
Xilinx FIR Compiler Fractional Rate Converter
Started by 3 years ago●4 replies●latest reply 7 months ago●161 viewsHello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...
Noise Generated using differential pmods as single ended
Started by 4 years ago●1 reply●latest reply 7 months ago●59 viewsHiI have a zedboard and a nexys video artix 7 board. I am generating a sinusoid from DDS Core of the same frequency (by supplying the same phase increment and the...
Using a single DSP48E2 Slice to infer three 48-bit inputs adder
Started by 4 years ago●1 reply●latest reply 7 months ago●180 viewsHi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(https://www.xilinx.com/support/answers/66429.html).I...
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal...
Lattice FPGA timing constraint help
Started by 3 years ago●5 replies●latest reply 7 months ago●248 viewsI have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior. I'm pretty sure it's due to timing constraint issues...
Aldec Active-HDL vs Modelsim PE state of play.
Started by 2 years ago●3 replies●latest reply 7 months ago●170 viewsWhat's the state of play here in 2021 ? I have had a Modelsim PE seat in maintenance for 16 years. Modelsim has not changed, improved any done anything in that...
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