Forums

Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 3 years ago10 replieslatest reply 1 month ago1111 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Use of DAC in ZCU111 Dev Board

Started by nicolas05 6 days ago5 replieslatest reply 5 days ago19 views
Hello Forum! ,I am a beginner with FPGA's. I want to implement an analog square wave generator using a ZCU111 Dev Board, but experiences with other boards can...

Some doubt about reset bridge

Started by nori 1 month ago1 replylatest reply 2 weeks ago24 views
Hi Forum,I am referring to this circuit:As you know it is well known circuit for pre-synchronizing reset (reset bridge).Looking into small details I imagine violation...
Hi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(https://www.xilinx.com/support/answers/66429.html).I...

I am new to FPGA, I need guidance to understand difference between UCF andXDC

Started by mekjayk 1 month ago2 replieslatest reply 1 month ago34 views
Hello everyone,I have kintex-7 based kit https://www.avnet.com/shop/us/products/xilinx/ek-k... . I started learning about FPGA using udemy courses. where pin placement...

Reusing registers in VHDL FSM code

Started by darian16 2 months ago5 replieslatest reply 2 months ago30 views
Hello, I need to write a Finite State Machine (FSM) in VHDL code and  want to have several computations being processed at the same time (a standard pipeline)....
HiI have a zedboard and a nexys video artix 7 board. I am generating a sinusoid from DDS Core of the same frequency (by supplying the same phase increment and the...

Tips for using Xilinx Ultra RAMs

Started by weetabixharry 2 months ago2 replieslatest reply 2 months ago33 views
What are the main considerations that I should be aware of if I want to use Ultra RAMs in my design?I am familiar with the Block RAMs used in 5-, 6- and 7-series...

recovery/removal violations, does it always matter?

Started by kaz 2 months ago9 replieslatest reply 2 months ago31 views
Hi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...

FPGA output pulsating in real time

Started by abdul_samad 2 months ago1 replylatest reply 2 months ago23 views
Hi,I am working on a digital down conversion module for a project of mine. The module down converts a  signal at IF 455 KHz received through an ADC, multiplies...

Registering will allow you to participate to the forums on ALL the related sites and give you access to all pdf downloads.

Sign up

I agree with the terms of use and privacy policy.

Try our occasional but popular newsletter. VERY easy to unsubscribe.
or Sign in