Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 5 years ago12 replieslatest reply 5 months ago1715 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Vivado Tcl

Started by Kocsonya 2 months ago3 replieslatest reply 2 months ago32 views
I'd like to use Vivado in non-project mode, using makefiles and Tcl scripts. However, my chip is a Zynq-7000 SoC where Vivado needs to generate a module representing...

set multicycle path contradiction on hold value

Started by kaz 4 months ago50 views
Trying to solve the following contradiction about "set_multicycle_path"case 1: "Vivado using constraints" pdf states that for most cases of timing relaxing multicycle...

FPGA speed and timing closure metrics

Started by kaz 5 months ago2 replieslatest reply 5 months ago42 views
We have plenty data sheets, documents, forum replies and videos on various fpgas and designs. However what is missing in all cases is some idea how fast can one...

Aldec Active-HDL vs Modelsim PE state of play.

Started by glenenglish 5 months ago2 replieslatest reply 5 months ago52 views
What's the state of play here  in 2021 ? I have had a Modelsim PE seat in maintenance for 16 years. Modelsim has not changed, improved any done anything in that...

Sha256 on FPGA board

Started by Iani97 5 months ago59 views
Hello guys,I have been trying to implement to implement the SHA256 algorithm on my ARTY A7 35t using VivadoI am using TeraTerm to send information to the board...

RC-filter in VHDL

Started by Aida92 6 months ago1 replylatest reply 6 months ago65 views
Hello everyone!I am trying to implement Raised-cosine filter in VHDL. In the current simulation I am using the standard method of the filter simulation:- create...

Doubt about constraining external input

Started by simonzz 8 months ago4 replieslatest reply 8 months ago42 views
Hi all,I am usig an AD9914 DDS its DROVER output connected to a I/O of the FPGA...

Implementing a folded FIR on FPGA

Started by DHMarinov 9 months ago2 replieslatest reply 8 months ago69 views
Hello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...

Efficient implementation of FIR filters on a FPGA

Started by DHMarinov 9 months ago2 replieslatest reply 9 months ago81 views
Hello there,I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here: PS:I'd...

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