Forums

Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 3 years ago10 replieslatest reply 5 months ago1196 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

HELP NEEDED - FPGA related Christmas present suggestions

Started by JB757 2 days ago1 replylatest reply 1 day ago23 views
Hi, I know nothing about FPGA, integrated circuits, electronics, et cetera. I do know that it's a field my father is interested in. A little background, he's worked...

DueProLogic by EarthPeopleTechnology: Help making it work?

Started by AwesomeCronk 2 weeks ago5 replieslatest reply 1 week ago27 views
I was given a DueProLogic(DPL) board last year as a birthday gift. I never could get it to work. After having built my desktop and having installed Quartus and the...

ML310 board by Xilinx

Started by rbeekhuijzen 2 weeks ago5 replieslatest reply 2 weeks ago32 views
Recently I came into the possession of a ML310 (Virtex-II Pro) board made by Xilinx. IT is an old board and unfortunately, except for a few User Guides nothing can...

Lattice MIPI-CSI2 IP

Started by stanzanim 1 month ago26 views
Due to lack of support from lattice - and also mi lack of experiece with Lattice: I come from the xlinx world - I am here to get help about integrating this IP on...

Timing paths from wires to registers

Started by kaz 1 month ago3 replieslatest reply 1 month ago23 views
Hi All,I 've come across this case (please see figure below) .I have a synchronous system but four constants (A,B,C,D) are implemented on wires and any one of them...
How to use non-dedicated IO pins as clock source to FPGA PLL or Clock MUX?I try to use "PROHIBIT PRIMARY" preference, as described in:TN1263 ECP5 and ECP5-5G sysCLOCK...

SPI core in EDK generates junk output

Started by shreeranjani 2 months ago23 views
Hi , I am working in Embedded Development Kit EDK 13.2 Virtex 5, on spi (one master one slave). Microblaze is operated at 50Mhz input clock. spi in edk is configured...

FT601Q: 245 Synchronous FIFO mode.

Started by atom1477 3 months ago1 replylatest reply 3 months ago43 views
Hi.I'm trying to use FT601Q with FPGA. But I have some loss of data. And I don't know if this is an error in my FPGA code, or an error in FT601Q chip. FT601Q have...

Lattice MachXO2 Timing errors.

Started by SpiderKenny 4 months ago4 replieslatest reply 3 months ago38 views
I have a pretty simple verilog project, in Lattice Diamond 3.11.My top module instantiates an OSCH (Lattice IP library) oscillator at 133 mhz, and a 'ws2812b' module...

Registering will allow you to participate to the forums on ALL the related sites and give you access to all pdf downloads.

Sign up

I agree with the terms of use and privacy policy.

Try our occasional but popular newsletter. VERY easy to unsubscribe.
or Sign in