It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Hello, All!I'm a professional software developer who is trying to make the jump into FPGA for fun, learning, and my own research purposes.  I've been studying the...

So far, we've been very good at staying on-topic in the *Related sites forums.  Today, let me break the trend and start a completely off-topic (#OT) thread that...

I am trying to generate the Aurora 8B10B core for Virtex-4 FPGA using ISE 14.7 in Windows 7  (64 bit) OS based on the procedure presented in LogiCore IP guide....

(a) I am prototyping a new CPU (Harvard Architecture) with separate 1MB  program memory and 1MB  data memory. Which Xilinx FPGA board would be the best choice...

I have 2 image files imported by ENVI tool (png or raster file), and they are stored in my hard disk, I want to transfer this data from host PC to target FPGA using...

I am currently at Embedded World in Germany (tomorrow is the last day) and with more than 1000 vendors, most relevant players in the industry are here this week.I...

A current active contract role for an FPGA engineer  is around but sounds very strange in that it tries to explain the FPGA more than the required skills for the...

Hi All,I am looking for any hints on  FPGA pin constraints and their PCB perspective.Are there any established rules for both designers (FPGA & PCB) to work...

Hello everyone,I would like to implement a bitrate regulation on an fpga board.Clock + data are incoming at bitrate with a +/- percentage. Then after a channel coder...