Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 2 years ago10 replieslatest reply 7 months ago894 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

Learning FPGA

Started by stephaneb 3 months ago18 replieslatest reply 6 days ago1060 views
A few months ago, this community tackled the first FPGA FAQ titled When (and why) is it a good idea to use an FPGA in your embedded system design?.  Your contributions...

Pink noise generator on FPGA

Started by keffe 1 week ago3 replieslatest reply 6 days ago94 views
Hello! I want to implement a pink noise generator for audio frequencies on an FPGA, using VHDL.However, i found that not much information on this, is to find. I...

getting started with high speed parallel to serial to parallel

Started by crazy_logic 1 week ago2 replieslatest reply 6 days ago20 views
Hi all, Would anyone have advice/guidance for myself in how to create a board taking 4 serial streams (think HDMI/DVI) and serialise them to send over one link...

replacement for XILINX XC3020A-7PC84C

Started by hamed_vrz 2 weeks ago3 replieslatest reply 2 weeks ago21 views
Hi Guys,I'm looking for an similar FPGA with XILINX XC3020A-7PC84C to replace with it.i want to do this replacement with minimum changes in circuit design.I checked...

Virtual (cycle accurate) CPU simulations

Started by strubi 2 weeks ago3 replieslatest reply 2 weeks ago60 views
Hi all, I've been hacking away on a CPU builder in the past years that allows to build a microcontroller kinda from scratch with some standard peripherals in...

MachXO2 I2C configuration. EFB I2C block synthesis error.

Started by atom1477 2 weeks ago2 replieslatest reply 2 weeks ago18 views
Hello.I creating project with LCMXO2-1200HC device in QFN32 package, so i have very limited number of IO pins and I want to configuring FPGA by I2C instead of JTAG.I...

How to understand -edge option if first edge of generated clock is falling edge?

Started by tip_can19 2 months ago1 replylatest reply 2 months ago28 views
I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like below:I...

What would be difference between clock latency and propagation delay?

Started by tip_can19 2 months ago4 replieslatest reply 2 months ago77 views
I believe the clock latency is the total time it takes from the clock source to an end point. Whereas, the propagation delay would simply be the delay between...

Activating CH7301 on SP605 board #xilinx #vhdl

Started by ajellis 3 months ago2 replieslatest reply 2 months ago42 views
HelloI am working on a project using the SP605 for a video application. Currently I'm trying to output a picture via the DVI output which is driven by a CH7301...

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