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Forums Update, Tips and Tricks - Please Read!
Started by 7 years ago●14 replies●latest reply 3 months ago●2671 viewsIt's been a few months since the launch of the new forums. Here are a few thoughts.
The thumbsup and beer buttons
If there is one thing that could have a...
Variable IIR-Filter Coefficient calculation in frequency domain
Started by 1 month ago●5 replies●latest reply 3 weeks ago●187 viewsHello,Currently im evaluating the usefulness of frequency domain filtering in FPGA for one of our projects. Im stuck with a problem that my limited knowledge of...
Adding Wi-Fi capability to a Pynq Z1 FPGA board by interfacing a Wi-Fi module
Started by 2 months ago●39 viewsI own a Pynq Z1 FPGA board without built-in Wi-Fi. How can I connect a Wi-Fi module, specifically using GPIO or communication interfaces like UART, SPI, or I2C?...
dynamically configure Xilinx FFT IP core
Started by 4 months ago●1 reply●latest reply 4 months ago●44 viewsHi all,My design uses Xilinx's FFT LogiCORE IP which I use to do FFT of transform length 128 points. I configure the IP core in Vivado GUI, instantiate in my code...
Is N-body simulation in O(n) time possible?
Started by 5 months ago●2 replies●latest reply 5 months ago●70 viewsHi! My name is Mason. I've recently been messing around with FPGAs, and I think I found a way to do N-body simulation in O(n) time. First, some quick background....
Hi All, I am starting to learn Verilog in order to program FPGAs. I have a project where I need to take three digital signals coming from three hall sensors on...
LZW or BWC Compression cores for FPGAs
Started by 1 year ago●1 reply●latest reply 7 months ago●59 viewsHello,Can anyone recommend RTL level cores for LZW or BWC compression/decompresison engines? Thank you.Best regards,Sanjay
Hello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...
Xilinx FIR Compiler Fractional Rate Converter
Started by 3 years ago●4 replies●latest reply 1 year ago●260 viewsHello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...
Noise Generated using differential pmods as single ended
Started by 5 years ago●1 reply●latest reply 1 year ago●76 viewsHiI have a zedboard and a nexys video artix 7 board. I am generating a sinusoid from DDS Core of the same frequency (by supplying the same phase increment and the...
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