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Forums Update, Tips and Tricks - Please Read!
Started by 2 years ago●10 replies●latest reply 3 months ago●772 viewsIt's been a few months since the launch of the new forums. Here are a few thoughts.
The thumbsup and beer buttons
If there is one thing that could have a...
Lattice: Utilization and Clock Report
Started by 3 weeks ago●3 replies●latest reply 1 week ago●16 viewsHello,I have only one clock in my design and the number of clock load in my clock report(.par) does not correspond to the number of the registers in the map report(.mrp),...
simple line drive generator doesn't work properly
Started by 2 weeks ago●3 replies●latest reply 1 week ago●22 viewsHi guysI don't have any real-world experience with synthesizable VHDL and FPGA's but I've been really curious about it for a long time. So I've found an old experimenter's...
Synchronizing clock cycles of FPGA in Mojo V3 with the clock cycle of a signal generator
Started by 1 month ago●4 replies●latest reply 4 weeks ago●60 viewsHi, So I want to synchronize the clock cycle of an FPGA in mojo V3 development board, whose default clock cycle is 50 MHz with a function generator. Currently,...
Hello! I am currently working on a matrix multiplication project. After performing the multiplication of the matrices, I am trying to build a module that can write...
VHDL Matrix Multiplication using UART and BRAM
Started by 2 months ago●2 replies●latest reply 2 months ago●52 viewsMy project involves performing matrix multiplication in vhdl. The two input matrices (8 bits each) are sent using a terminal and received via UART Rx. The FPGA...
Implementing octave algorithm in FPGA using c++
Started by 2 months ago●11 replies●latest reply 2 months ago●171 viewsI am currently working on writing a scrambler and DeScrambler code for Orthogonal Frequency Division Multiplexing(OFDM). I am planning to write an algorithm for...
Searching for info about very old FPGA devices
Started by 3 months ago●3 replies●latest reply 3 months ago●54 viewsHello. My name is Rodrigo and I am from Argentina. I was looking for very old datasheets without success :-( (I searched a lot in google, archive.org, alldatasheets,...
I am looking at a tool (or combination of tools) to perform the following. Please advise.1) Read Verilog/VHDL RTL input code and convert it to technology independent...
Mux versus internal high impledance
Started by 3 months ago●5 replies●latest reply 3 months ago●46 viewsHi,
I have been an FPGA designer for more than a decade now and tutor a class on FPGA design at University presently. In all these years, I have had two ways of...
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