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Forums Update, Tips and Tricks - Please Read!
Started by 8 years ago●12 replies●latest reply 3 months ago●2901 viewsIt's been a few months since the launch of the new forums. Here are a few thoughts.
The thumbsup and beer buttons
If there is one thing that could have a...
A few months ago, this community tackled the first FPGA FAQ titled When (and why) is it a good idea to use an FPGA in your embedded system design?. Your contributions...
Variable IIR-Filter Coefficient calculation in frequency domain
Started by 7 months ago●6 replies●latest reply 4 months ago●349 viewsHello,Currently im evaluating the usefulness of frequency domain filtering in FPGA for one of our projects. Im stuck with a problem that my limited knowledge of...
Adding Wi-Fi capability to a Pynq Z1 FPGA board by interfacing a Wi-Fi module
Started by 8 months ago●58 viewsI own a Pynq Z1 FPGA board without built-in Wi-Fi. How can I connect a Wi-Fi module, specifically using GPIO or communication interfaces like UART, SPI, or I2C?...
dynamically configure Xilinx FFT IP core
Started by 10 months ago●1 reply●latest reply 10 months ago●90 viewsHi all,My design uses Xilinx's FFT LogiCORE IP which I use to do FFT of transform length 128 points. I configure the IP core in Vivado GUI, instantiate in my code...
Is N-body simulation in O(n) time possible?
Started by 11 months ago●2 replies●latest reply 11 months ago●86 viewsHi! My name is Mason. I've recently been messing around with FPGAs, and I think I found a way to do N-body simulation in O(n) time. First, some quick background....
Hi All, I am starting to learn Verilog in order to program FPGAs. I have a project where I need to take three digital signals coming from three hall sensors on...
LZW or BWC Compression cores for FPGAs
Started by 2 years ago●1 reply●latest reply 1 year ago●79 viewsHello,Can anyone recommend RTL level cores for LZW or BWC compression/decompresison engines? Thank you.Best regards,Sanjay
Implementing a folded FIR on FPGA
Started by 4 years ago●5 replies●latest reply 2 years ago●198 viewsHello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...
Xilinx FIR Compiler Fractional Rate Converter
Started by 4 years ago●4 replies●latest reply 2 years ago●413 viewsHello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...
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