It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

I am working on a project using the cyclone V from Altera. The FPGA has 3.3v GPIO pins and I would like to know what I could use to mimic a GPIO pins output. I am...

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I am designing the FIR filter for up conversion in FPGA. Input to the FIR filter is 16 bits wide (-32768 to 32767) with the maximum co-eff value of 32767. This produces...

Hello, What's the difference between Programmable SoC and SoC FPGA ?  Thank you

Hi, my name is IMA and I am now studying about the FPGA VHDL language to generate the gate signal for my converter circuit. I have basic C++ programming...

I put in a support ticket with Lattice. Nothing they suggested I try worked. Except installing on another Windows box. When I did not get the error on the other...

If I implemented the new email notification system well, this new thread should trigger an email notification to all members who have been approved to participate...

I wonder what are the guidelines for porting ASIC RTL to FPGA for emulation.1. Memory blocks need be adjusted for FPGA device specific features.2. DSP Elements...

Hi allI'm going to work with high speed ADC in my upcoming project. I'm having 4 ADC channels with 3.2GHz sampling rate interfaced with FPGA. I'm getting 40 samples...