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Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 5 years ago11 replieslatest reply 7 months ago1591 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

RC-filter in VHDL

Started by Aida92 1 month ago1 replylatest reply 4 weeks ago38 views
Hello everyone!I am trying to implement Raised-cosine filter in VHDL. In the current simulation I am using the standard method of the filter simulation:- create...

Doubt about constraining external input

Started by simonzz 2 months ago4 replieslatest reply 2 months ago35 views
Hi all,I am usig an AD9914 DDShttps://www.analog.com/media/en/technical-documentation/data-sheets/AD9914.pdfwith its DROVER output connected to a I/O of the FPGA...

Implementing a folded FIR on FPGA

Started by DHMarinov 4 months ago2 replieslatest reply 3 months ago46 views
Hello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...

Efficient implementation of FIR filters on a FPGA

Started by DHMarinov 4 months ago2 replieslatest reply 4 months ago52 views
Hello there,I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here: PS:I'd...

Xilinx FIR Compiler Fractional Rate Converter

Started by ismailt42 4 months ago1 replylatest reply 4 months ago30 views
Hello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...

Polyphase Filter Bank channelizer issue

Started by epetragl 6 months ago5 replieslatest reply 5 months ago224 views
Hello, I am currently studying the implementation of a Polyphase Filter Bank channelizer designed by Xilinx in its XAPP1161. The architecture is composed by a single...

UART communication For Nexys A7-100t

Started by MCU231 6 months ago1 replylatest reply 5 months ago88 views
Hello,I'm new to UART for FPGA and recently I tried a demo project that I found at: https://www.fpga4fun.com/SerialInterface.htmlMy problem is using RxD_data_ready...

Zedboard and the ov7670 settings

Started by shlomishab 6 months ago51 views
I've been working on a video streaming project using a zedboard and the ov7670 camera. My project is based on this one (capture and vga .vhd files): https://www.hackster.io/dhq/fpga-camera-system-14d6ea...

Attempting to implement UART - Unexpected Behaviour

Started by fayalalebrun 7 months ago9 replieslatest reply 7 months ago61 views
I have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to implement the...

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