Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology)
Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing as novel FPGA families are replacing ASICs and PDSPs for front-end digital signal processing algorithms. So the efficient implementation of these algorithms is critical and is the main goal of this book. It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems. A case study in the first chapter is the basis for more than 30 design examples throughout. The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, and advanced algorithms with high future potential. Each chapter contains exercises. The VERILOG source code and a glossary are given in the appendices, while the accompanying CD-ROM contains the examples in VHDL and Verilog code as well as the newest Altera "Baseline" software. This edition has a new chapter on adaptive filters, new sections on division and floating point arithmetics, an up-date to the current Altera software, and some new exercises.
Why Read This Book
You should read this book if you want a hands-on bridge from DSP algorithms to FPGA implementations — it walks through arithmetic choices, architectures and optimisation strategies and includes Verilog examples you can synthesise. It’s especially useful when you need practical recipes for mapping filters, FFTs and multirate blocks onto FPGA resources.
Who Will Benefit
FPGA and DSP engineers or graduate students who already know DSP fundamentals and want to implement efficient FIR/IIR, FFT and multirate designs in hardware using Verilog on Xilinx/Altera-class FPGAs.
Level: Intermediate — Prerequisites: Basic DSP (filters, FFT/DFT), digital logic fundamentals, and familiarity with Verilog or another HDL and an FPGA toolflow (synthesis/simulation).
Key Takeaways
- Design and implement fixed-point computer arithmetic suitable for FPGA DSP workloads, including scaling and quantization strategies.
- Implement efficient FIR filter architectures (direct, transposed, symmetric, polyphase) mapped to FPGA primitives.
- Implement IIR filters and understand stability, precision and implementation trade-offs on FPGAs.
- Design and synthesise pipelined and memory-efficient FFT/DFT implementations for FPGA resources.
- Implement multirate systems (decimation/interpolation, polyphase structures) and optimize them for throughput and area.
- Translate DSP algorithmic choices into resource-aware Verilog that targets block RAMs, DSP slices and routing constraints.
Topics Covered
- Introduction and FPGA technology overview (devices, families, toolflows)
- Case study: system requirements and top-level FPGA design
- Computer arithmetic: fixed-point representation, rounding, overflow, and scaling
- FIR filter theory and FPGA implementations (architectures and optimisations)
- IIR filters: structures, numerical issues, and hardware mapping
- Multirate signal processing: decimation, interpolation and polyphase implementations
- DFT and FFT algorithms: radix techniques, pipelining and resource trade-offs
- Advanced DSP algorithms with FPGA potential (e.g., filtering banks, overlap-save)
- Practical design examples and exercises (synthesis-ready Verilog)
- Verification, simulation, and implementation notes (timing, quantization tests)
- Appendices: Verilog source listings and recommended tools
Languages, Platforms & Tools
How It Compares
Similar in scope to Roger Woods et al.'s 'FPGA-based Implementation of Signal Processing Systems' but Meyer‑Baese focuses more on algorithm-architecture tradeoffs and fixed-point arithmetic with ready Verilog examples, while Woods et al. lean more into toolflow and system-level case studies.
