How to do Math's in FPGA - Using VHDL 2008

Adam Taylor

Still RelevantIntermediate

Following the introduction of VHDL 93, which introduced the numeric_std package and the signed and unsigned types, implementing fixed point maths has been fairly straight forward. Using this package, we can implement mathematics using a fixed point representation. However, to implement a fixed point algorithm we need to understand the simple rules regarding fixed point operations.

Summary

This article explains how to implement fixed-point mathematics in VHDL 2008 using the numeric_std package and the signed/unsigned types. It teaches the basic rules for fixed-point operations, resizing, alignment, and synthesis-friendly coding for FPGA DSP applications.

Key Takeaways

Understand fixed-point representation and scaling rules in VHDL 2008 using numeric_std
Apply signed and unsigned types correctly and perform alignment, resizing, and rounding for arithmetic ops
Handle overflow and implement saturation or wrapping strategies appropriate for hardware
Estimate synthesis implications on FPGA resources and map arithmetic to DSP blocks effectively
Write testbenches and synthesis-friendly VHDL that produce predictable fixed-point behavior

Who Should Read This

Intermediate FPGA engineers and designers working with VHDL who need practical guidance on implementing fixed-point DSP algorithms and ensuring synthesis-friendly math operations.

Still RelevantIntermediate