The Designer's Guide to VHDL, Volume 3, Third Edition
VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.
* First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard...helps readers get up to speed quickly with new features of the new standard.
* Presents a structured guide to the modeling facilities offered by VHDL...shows how VHDL functions to help design digital systems.
* Includes extensive case studies and source code used to develop testbenches and case study examples..helps readers gain maximum facility with VHDL for design of digital systems.
Why Read This Book
You should read this book if you need a deep, practical, and standards-aware guide to VHDL — including the VHDL-2008 additions — that ties language detail to real design and verification practice. It combines clear explanations, rules for synthesis vs. simulation, and extensive example code so you can apply features correctly in FPGA and ASIC projects.
Who Will Benefit
Practicing digital designers and verification engineers who write or review VHDL for FPGA/ASIC projects and want a comprehensive, standards-based reference and cookbook.
Level: Intermediate — Prerequisites: Basic digital logic and sequential design concepts; some prior exposure to an HDL (preferably VHDL) or programming experience will help you get the most from the book.
Key Takeaways
- Apply the VHDL-2008 language features correctly, including new data types and synthesis-friendly constructs.
- Distinguish synthesizable RTL constructs from simulation-only modeling and write portable, synthesisable code.
- Design modular components using packages, generics, configurations, and hierarchical design techniques.
- Build robust testbenches using processes, stimulus generation, assertions, and recommended verification idioms.
- Translate behavioral descriptions into efficient hardware by understanding concurrency, timing, and signal semantics.
- Use case-study examples to structure real designs and learn practical pitfalls and best practices.
Topics Covered
- Introduction and history of VHDL / overview of VHDL-2008
- Lexical conventions, identifiers and comments
- Data types, type declarations and type conversions
- Concurrent statements, signal assignment and signal drivers
- Sequential statements, processes and subprograms
- Packages, libraries, units and design hierarchy
- Generics, configurations and component instantiation
- Synthesis considerations and synthesizable subset
- Verification techniques: testbenches, assertions and simulation
- Advanced types and utilities (records, unconstrained arrays, protected types)
- VHDL-2008 new features and enhancements
- Modeling examples and case studies
- Guidelines, coding style and migration advice
Languages, Platforms & Tools
How It Compares
More thorough and standards-focused than Douglas Perry's 'VHDL: Programming by Example' and more formal and comprehensive than introductory primers such as 'A VHDL Primer' — Ashenden is the go-to reference for VHDL-2008 details.
