Fundamentals of Digital Logic with Verilog Design
Fundamentals of Digital Logic With Verilog Design teaches the basic design techniques for logic circuits. It emphasizes the synthesis of circuits and explains how circuits are implemented in real chips. Fundamental concepts are illustrated by using small examples.
Use of CAD software is well integrated into the book. A CD-ROM that contains Altera's Quartus CAD software comes free with every copy of the text. The CAD software provides automatic mapping of a design written in Verilog into Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Students will be able to try, firsthand, the book's Verilog examples (over 140) and homework problems.
Engineers use Quartus CAD for designing, simulating, testing and implementing logic circuits. The version included with this text supports all major features of the commercial product and comes with a compiler for the IEEE standard Verilog language. Students will be able to:
enter a design into the CAD system
compile the design into a selected device
simulate the functionality and timing of the resulting circuit
implement the designs in actual devices (using the school's laboratory facilities)
Verilog is a complex language, so it is introduced gradually in the book. Each Verilog feature is presented as it becomes pertinent for the circuits being discussed. To teach the student to use the Quartus CAD, the book includes three tutorials.
Why Read This Book
You should read this book if you want a structured introduction that connects digital-logic theory to real HDL practice: you will learn Verilog coding, simulation, and how synthesized designs map onto FPGAs/CPLDs. The book pairs clear explanations with hands-on CAD labs and many worked examples so you can move quickly from concept to tested hardware.
Who Will Benefit
Undergraduate students and early-career engineers who need a practical, synthesis-focused introduction to digital logic and Verilog with FPGA implementation experience.
Level: Beginner — Prerequisites: Basic algebra and familiarity with binary/Boolean concepts; no prior Verilog or FPGA experience required.
Key Takeaways
- Describe and apply Boolean algebra and minimization techniques to design combinational logic.
- Write, simulate, and debug structural and behavioral Verilog for combinational and sequential circuits.
- Design and implement finite-state machines and synchronous datapaths in Verilog.
- Synthesize Verilog designs and map them to FPGAs/CPLDs using a CAD flow (Altera Quartus).
- Analyze basic timing, resource usage, and practical implementation trade-offs for FPGA targets.
Topics Covered
- Introduction to Digital Systems and Design Methodology
- Number Systems, Binary Arithmetic, and Boolean Algebra
- Combinational Logic Design and Minimization
- Verilog Language Essentials: Data Types and Modeling Styles
- Modeling Combinational Logic in Verilog
- Sequential Logic: Flip-Flops, Registers, and Timing
- Design of Finite State Machines in Verilog
- Registers, Counters, and Common Sequential Circuits
- Memory, Buses, and I/O Interfaces
- Synthesis Concepts and Mapping to PLDs/FPGA Architectures
- Using CAD Tools: Altera Quartus Labs and Design Flow
- Timing, Clocking, and Practical Implementation Issues
- Testing, Simulation, and Debugging Techniques
- Project Examples and Laboratory Exercises
Languages, Platforms & Tools
How It Compares
Covers similar undergraduate ground to M. Morris Mano's Digital Design but adds hands-on Verilog and FPGA synthesis; compared to Samir Palnitkar's Verilog HDL, Brown's book is more of a course textbook with labs rather than a concise language reference.
