ddr with multiple users

Started by David Ashley in comp.arch.fpga11 years ago 27 replies

Hi, I have about 4 different independent things that each need to access a ddr. On one hand it seems I can make them all...

Hi, I have about 4 different independent things that each need to access a ddr. On one hand it seems I can make them all wishbone compliant then just have a wishbone ddr interface. Would be workable/advisable to instead just have each device control the ddr itself, and use the ddr's own interface directly? I'd only need one complicated mechanism to initialize the ddr after reset, b...


DDR FPGA Design

Started by Mounard Le Fougueux in comp.arch.fpga11 years ago 11 replies

I'm planning an FPGA design that will be using SDRAM (DDR Winbond W9425G6DH5) and NAND Flash (ST NAND018W3B2AN6E). I'm not particularly...

I'm planning an FPGA design that will be using SDRAM (DDR Winbond W9425G6DH5) and NAND Flash (ST NAND018W3B2AN6E). I'm not particularly experienced in DDR memory design and there are other issues that need my attention other then just DDR RAM design. I keep hearing horror stories about engineers getting into trouble with DDR RAM designs. Do you have any experience integrating DDR to FPG...


Addressing DDR-RAM

Started by Thomas in comp.arch.fpga11 years ago 2 replies

Hello, I've got a Xilinx Virtex 4 FPGA and would like to address the onboard DDR-SDRAM. I've found out that I can instantiate special DDR-IO...

Hello, I've got a Xilinx Virtex 4 FPGA and would like to address the onboard DDR-SDRAM. I've found out that I can instantiate special DDR-IO flip flops by hand (and found an example in the ISE-Webpack documentation). But I'm still not sure how to address the DDR-SDRAM best, especially I don't know how to handle the DQS-Signal of the DDR-SDRAM, because I need a sensitivity on both edges....


DDR Termination

Started by maxascent in comp.arch.fpga12 years ago 1 reply

I am creating a design using a Xilinx Virtex II Pro and some DDR memory. I downloaded the Xilinx ML361 DDR Ref design to get some tips. They...

I am creating a design using a Xilinx Virtex II Pro and some DDR memory. I downloaded the Xilinx ML361 DDR Ref design to get some tips. They have put resistors on the appropriate tracks to VTT at both the DDR and FPGA. I was going to put the resistor at the DDR but use the FPGAs DCI to terminate at the FPGA using a series resistance. Can I do this or have I missed a trick somewhere along. Che...


Virtex-4 DDR RAM Usage (with VHDL)

Started by Elmar Weber in comp.arch.fpga11 years ago

Hello, I'm trying to access the DDR SDRAM of a Virtex-4 ML403 Evaluation board (XC4VFX12-10). I downloaded the reference implementation...

Hello, I'm trying to access the DDR SDRAM of a Virtex-4 ML403 Evaluation board (XC4VFX12-10). I downloaded the reference implementation from the Xilinx Homepage, removed the ICON and ILA parts and synthesized it. The upload to the FPGA worked without problems and it accessed the DDR RAM (at least the DDR RAM heated up). After reading the reference design specification and the DDR ...


Minimum frequency at which ddr can operate

Started by subint in comp.arch.fpga11 years ago 4 replies

Hi, I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga. And i am using the controller generated by the MIG1.5 tool. When i...

Hi, I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga. And i am using the controller generated by the MIG1.5 tool. When i run this controller in the real hardware i am getting zeros in the result bus(read_data_fifo_out)... Dont know where i am wrong. I am monitored all my controller signals using the chipscope and they are all working fine for me. But the ddr is n...


DDR Controller

Started by yy in comp.arch.fpga11 years ago 4 replies

Hi, I am to build a fpga system that captures data from external signals and store it to DDR, also after the capture data must be transferred...

Hi, I am to build a fpga system that captures data from external signals and store it to DDR, also after the capture data must be transferred to the PC via PCI bus via DMA or so. So this is a CAPTURE-to-DDR DDR-to-PCI... How is this sytem implemented?


Strange ddr controller bugs.

Started by dada...@gmail.com in comp.arch.fpga9 years ago 6 replies
DDR

Hi all: I am meet a very strange ddr controller bugs on board. since system power up. I turn on the ddr controller tester to test the DDR...

Hi all: I am meet a very strange ddr controller bugs on board. since system power up. I turn on the ddr controller tester to test the DDR interface of FPGA(virtex5), after a long time run it appers just fine. but when I reset the FPGA. and run the tester again, I got errors when read back data from DDR. and I want to know does reset FPGA can cause the unstable working of DDR controller? s...


Xilinx EDK 8.1 DDR controller behavior

Started by Antti in comp.arch.fpga12 years ago 3 replies

Hi does anyone know what should happen on read access to DDR memory space when external connections to DDR memory are not correct? I am...

Hi does anyone know what should happen on read access to DDR memory space when external connections to DDR memory are not correct? I am troubleshooting a custom board and what I see is that OPB DDR controller makes total OPB bus freeze on first DDR read access. ToutSup=1 and then nothing happens. In the datasheet DQS strobe is going to WREN of read fifo so I could think a missing DQS from...


Virtex II LVDS plus DDR?

Started by Mark in comp.arch.fpga13 years ago 1 reply

Howdy Gurus, I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS i/o and their DDR i/o, but haven't found a clear...

Howdy Gurus, I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS i/o and their DDR i/o, but haven't found a clear explanation yet of the two being used together. DDR by itself is pretty obvious, but the LVDS appears to work by a magical connection between two neighboring IOBs. For an LVDS input pair (Dp and Dn) coming in at DDR, does the differential-to-single-ended ...


Why 166Mhz DDR?

Started by Anonymous in comp.arch.fpga11 years ago 9 replies
DDR

Hi, I was wondering how the number 166Mhz for DDR came up? Why not say... 200MHz/250MHz DDR? I am sure there is some thought process...

Hi, I was wondering how the number 166Mhz for DDR came up? Why not say... 200MHz/250MHz DDR? I am sure there is some thought process behind that, could someone help me walk through? Thanks in advance ! -Rohit


Simulation problem for the DDR controller

Started by subint in comp.arch.fpga11 years ago 1 reply

Hi, I am using the DDR controller(generated by MIG1.5) for the ddr MT46V32M16 -6 for the board V4MBlx60. I am getting the expected result in...

Hi, I am using the DDR controller(generated by MIG1.5) for the ddr MT46V32M16 -6 for the board V4MBlx60. I am getting the expected result in simulation with the hdl code generated by the MIG.But when i tried to simulate the post-par model of the code all interfaces to the ddr are driven with x.Any idea. thanks in advance subin


Spartan3E - problem in creating LVDS DDR pads

Started by Anonymous in comp.arch.fpga12 years ago 3 replies

Hi all, I am trying to create LVDS, bidirectional, DDR I/O pads in a Spartan-3E chip (xc3s500e). I've created an I/O pad in VHDL which...

Hi all, I am trying to create LVDS, bidirectional, DDR I/O pads in a Spartan-3E chip (xc3s500e). I've created an I/O pad in VHDL which simply instatiates and connects Xilinx library components: * IOBUFDS = bidirectional, differential I/O pad, * IDDR2 = S3E input DDR logic, * ODDR2 = S3E output DDR logic, Tri-State control is not DDR - I've added a simple FF instance. The pad ...


Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a

Started by Nju Njoroge in comp.arch.fpga12 years ago 2 replies

Hello, Is there an existing flow for simulating PLB DDR in ModelSim using EDK 7.1 SP2 in a full system (PPCs, pcores,etc)? The instructions...

Hello, Is there an existing flow for simulating PLB DDR in ModelSim using EDK 7.1 SP2 in a full system (PPCs, pcores,etc)? The instructions are being stored in BRAMs, as to avoid DDR initialization hassles. I have been simulating the data-only DDR using BRAMs, however, to get a more accurate depiction of the system, I would like to use DDR in simulation. Thanks, NN


DDR Controller Blue

Started by Digital Mike in comp.arch.fpga11 years ago 5 replies
DDR

Dear all, I am working on a DDR controller that stores captured video frames from which a VGA controller retrieves data. It (DDR controller)...

Dear all, I am working on a DDR controller that stores captured video frames from which a VGA controller retrieves data. It (DDR controller) works fine for the first few frames but seems dead afterward. I wonder if anyone experienced similar problem. What I did (for initial testing purpose) is to capture and store a frame into the DDR then retrieve the same frame (a 640x480 pixels area) ov...


ML402 card (video starter kit) : Read/write on the ddr

Started by hammouda in comp.arch.fpga10 years ago 1 reply
DDR

Hello everybody, I am trying to make a software video processing with the VSK. For this, I want read video data from the DDR, applied the...

Hello everybody, I am trying to make a software video processing with the VSK. For this, I want read video data from the DDR, applied the convolution algorithm and write the modified video data in the ddr. but I have some probleme to read/write in the ddr. Can anyone tell me how we can read and write data in the ddr? Thanks.


opb_ddr connection to DDR chips

Started by Sylvain Munaut in comp.arch.fpga13 years ago 4 replies

Hello I'm planning to do a microblaze design using external DDR memory using the opb_ddr core. However I'd like to know if there is any...

Hello I'm planning to do a microblaze design using external DDR memory using the opb_ddr core. However I'd like to know if there is any constraints on how to connect (which banks/pins ...) the DDR chip. Here I only have 1 point to point connection of a 16 bits wide DDR. I was planning on using two banks for all the DQS/DQM/DQ then another bank for the control & address signals. I have...


Ddr sdram feedback pin

Started by Pablo in comp.arch.fpga10 years ago 4 replies

Hi everyone, I want to design a model with my Smt338. This is a Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16 as DDR...

Hi everyone, I want to design a model with my Smt338. This is a Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16 as DDR memory. First of all I need to implement the hardware architecture, so I use edk 8.1 (or edk 8.2) to create a model with PowerPC and this DDR memory. In the ucf I map every port, but I have not any pin to DDR_CLK, that is, the feedback ddr clock. This ...


Transfering image file to DDR RAM using EDK

Started by rashmic in comp.arch.fpga3 years ago 1 reply

Hi, I am working on Xilinx Spartan 3e Starter kit board which has DDR Ram. I have to transfer image file to DDR and store it for further...

Hi, I am working on Xilinx Spartan 3e Starter kit board which has DDR Ram. I have to transfer image file to DDR and store it for further manipulation using EDK.Please provide different techniques to transfer files in ddr using EDK. -- rashmic http://compgroups.net/comp.arch.fpga/


ddr clock issues

Started by David Ashley in comp.arch.fpga11 years ago 17 replies

Open Cores DDR controller uses 2 DCM's to generate the clocks. clk -> dcm0 -> clock used for fddr to produce true + negative ddr clocks ...

Open Cores DDR controller uses 2 DCM's to generate the clocks. clk -> dcm0 -> clock used for fddr to produce true + negative ddr clocks feedback comes from true ddr clock fddr has hard wired 01 inputs for true clock, 10 inputs for negative clock clk -> dcm1 -> (0 clock) bufg1 -> clock used for all ddr related inter