Verilog books

Started by Alex Weddell in comp.arch.fpga13 years ago

Hi, Can anyone recommend a good book on verilog? I've got some experience with VHDL, but am looking for a book on verilog with an emphasis on...

Hi, Can anyone recommend a good book on verilog? I've got some experience with VHDL, but am looking for a book on verilog with an emphasis on synthesisable design. Inclusion of the verilog 2001 additions would also be nice! Thanks in advance, Alex


Newbie Verilog Question / ModelSim

Started by RL in comp.arch.fpga9 years ago 4 replies

Hi, I am thinking of using Verilog for a project I am working on. Originally I was going to use a processor core (and C) on an environment...

Hi, I am thinking of using Verilog for a project I am working on. Originally I was going to use a processor core (and C) on an environment someone set up for me in VHDL/Verilog, then I thought of using FpgaC and doing it myself, and now I'm more or less decided on using Verilog to do most of it (minus the hardware stuff, after initial development and simulation). My first questions, ...


verilog task and vhdl

Started by carlob in comp.arch.fpga6 years ago 10 replies

Hi all, I've a functional model of a PHY chip in verilog with a lot of tasks to stimualte change on signals at the interface (and not...

Hi all, I've a functional model of a PHY chip in verilog with a lot of tasks to stimualte change on signals at the interface (and not only)... Unfortunately I'm not experienced with verilog...I would write a testbench in vhdl and reuse the model in verilog... How to call a verilog task inside a vhdl testbench??? Is it possible??? I would like to don't change the verilog (that has already been...


Synthesis in VHDL vs. Verilog

Started by Chris Carlen in comp.arch.fpga14 years ago 28 replies

Greetings: I am reading J Bhasker's "Verilog HDL Synthesis" along with "A Verilog Primer" in order to learn not only Verilog, but how to make...

Greetings: I am reading J Bhasker's "Verilog HDL Synthesis" along with "A Verilog Primer" in order to learn not only Verilog, but how to make sure I can model designs in a way that is synthesizable. What I have just learned is that the synthesis system (such as if I am using Xilinx ISE Webpack and it's associated synthesis tools) dictates what style must be followed, because one syst...


Verilog tutorial by John Sanguinetti

Started by Eric Crabill in comp.arch.fpga12 years ago 4 replies

Hi, I'm looking for a functional URL that hosts the Verilog tutorial by John Sanguinetti. Neither of these seem to...

Hi, I'm looking for a functional URL that hosts the Verilog tutorial by John Sanguinetti. Neither of these seem to work: http://turing.une.edu.au/~comp283/cdrom/Content/Tutorials/Verilog/ http://vol.verilog.com/ I have tried contacting what appears to be the primary/official site (vol.verilog.com) and have received no responses. Is anyone aware of other URLs or how to get this tu...


Atmel CPLD development tools for verilog

Started by sri in comp.arch.fpga12 years ago

Hi, Currently I have verilog design files ready for a CPLD implementation and am planning to use a Atmel AT15xx series CPLD. But I am...

Hi, Currently I have verilog design files ready for a CPLD implementation and am planning to use a Atmel AT15xx series CPLD. But I am having difficulty in finding the right Atmel development software. As per the Atmel website, Prochip supports Verilog, but when installed I am not able to compile the Verilog design. Is there any other tool I can use to get the edif file from my Verilog...


Verilog, VHDL, sync and async resets

Started by johnp in comp.arch.fpga6 years ago 1 reply

We need to code some modules in both VHDL and Verilog and would like to use a parameter/generic to control inferring sync or async resets. Is...

We need to code some modules in both VHDL and Verilog and would like to use a parameter/generic to control inferring sync or async resets. Is there a clean way to code this that is similar in both VHDL and Verilog? For example, we could try to use `define in Verilog, but this won't port well to VHDL. I don't see how wen can use generate statements in Verilog to do this nicely, either. ...


learning verilog

Started by kristoff in comp.arch.fpga1 year ago 7 replies

Hi all, I am currently learning VHDL step by step, but I noticed there are also quite a lot of projects written in verilog. So, for...

Hi all, I am currently learning VHDL step by step, but I noticed there are also quite a lot of projects written in verilog. So, for somebody who knows the basis, what would be best? - First get a very good knowledge of VHDL and then start with verilog - or learn vhdl and verilog at the same time (as the two languages do offer simular features). Kristoff


Verilog Book for VHDL Users

Started by rickman in comp.arch.fpga7 years ago 22 replies

I am finally going to learn Verilog for real after using VHDL for 15 years. I've done a little work with Verilog and found it relatively easy...

I am finally going to learn Verilog for real after using VHDL for 15 years. I've done a little work with Verilog and found it relatively easy to use. Now I want to learn the details and especially how not to make mistakes. VHDL has the problem of not letting you do things unless you make it explicitly clear what you want to do. My understanding is that Verilog will let you not specify f...


Call VHDL module from Verilog

Started by egadget1 in comp.arch.fpga10 years ago 2 replies

Hi, I have a basic question. Is is possible in the xilinx ISE enviroment to make a verilog wrapper of some VHDL code. I don't want to...

Hi, I have a basic question. Is is possible in the xilinx ISE enviroment to make a verilog wrapper of some VHDL code. I don't want to recode it in verilog. Thanks Rob


Is it possible to have a parameterized verilog module name in verilog or systemverilog?

Started by Anonymous in comp.arch.fpga2 years ago 6 replies

Hi, I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things...

Hi, I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things can be parameterized. But can we also parameterize the module instance name? In following code, I am curious if there is any way SomeDynamicInstanceName can be parameterized also? I can try to use system verilog if that can help here M


Verilog Ref Book

Started by hdl_book_seller in comp.arch.fpga11 years ago 1 reply

We have about 34 copies left of the most popular Verilog reference book, Thomas & Moorby's classic "The Verilog Hardware Language" at only $32...

We have about 34 copies left of the most popular Verilog reference book, Thomas & Moorby's classic "The Verilog Hardware Language" at only $32 -- over 73% off the Amazon price of $119. We have sold hundreds of these books to chip designers and students worldwide. This classic Verilog reference text is brand new and in the original plastic wrapper, WITH CDROM. We ship with free Priority Ma...


Verilog vs VHDL for Loops

Started by Andre Bonin in comp.arch.fpga13 years ago 13 replies

Hey all, I'me trying to convert a C algorithm to Verilog using Quartus II Web edition. The following for loop doesn't compile because it says...

Hey all, I'me trying to convert a C algorithm to Verilog using Quartus II Web edition. The following for loop doesn't compile because it says its not of constant loop time. What i really need is to be able to calculate the loop time "on the fly". Can VHDL or Verilog do this? or is this a limitation? Thanks Error: Verilog HDL For Statement error at XXXXXXXX.v(49): must use only ...


Verilog and VHDL mix

Started by Remis Norvilis in comp.arch.fpga14 years ago 4 replies

I wonder if it is possible to synthesize on one chip VHDL and Verilog IP cores. I suppose the VHDL to Verilog or vice versa translator could...

I wonder if it is possible to synthesize on one chip VHDL and Verilog IP cores. I suppose the VHDL to Verilog or vice versa translator could be used. Ideas are welcome. Remis -- ************************************************ To reply, remove > .spam < and > .fake <


Verilog module in VHDL project - ISE 13

Started by Mike Harrison in comp.arch.fpga6 years ago 1 reply

I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in Verilog, in a new VHDL project, as I'm much...

I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in Verilog, in a new VHDL project, as I'm much more familiar with VHDL - I don't do enough FPGA stuff to justify the time to learn a new language for one project. Can anyone point me towards how I can include the verilog modules and make the signals visible to my VHDL - any example of a verilog ...


Virtex-4 ML403 16x2 LCD

Started by Shela in comp.arch.fpga11 years ago 1 reply

HI all, I am a student. I am new to verilog and FPGA. I have a question. How do I use the 16x2 LCD which is on the development board? I...

HI all, I am a student. I am new to verilog and FPGA. I have a question. How do I use the 16x2 LCD which is on the development board? I have a verilog code which I want the LCD to load the ASCII char from the verilog code I written. The verilog code is just a few shift register acting like a LUT (look up table). Is there any way i can control the 16x2 LCD or is there any macro? I r...


Good, affordable verilog simulator

Started by Paul Taddonio in comp.arch.fpga13 years ago 11 replies

Can anybody recommend a good PC-based verilog simulator for substantially less than $4500? I am a new hire at a company which spent big bucks...

Can anybody recommend a good PC-based verilog simulator for substantially less than $4500? I am a new hire at a company which spent big bucks on ModelSim just two years ago. Unfortunately we purchased VHDL and I am a verilog designer. We have a tight schedule so I will stick with the familiar language. I would use the VHDL simulator but Xilinx tools won't put out a VHDL model from verilog sourc...


VHDL or Verilog

Started by Clemens Hagen in comp.arch.fpga13 years ago 6 replies

Hello I have a very basic question. Normally you have the choice if you want to use VHDL or Verilog for describing you hardware...

Hello I have a very basic question. Normally you have the choice if you want to use VHDL or Verilog for describing you hardware architecture. I would be interested when do you decide for VHDL and when for Verilog. Are the special cases when it makes more sense to use one or the other language? Thanks for helpful tips Clemens


Perl Preprocessor for HDL

Started by Kevin Neilson in comp.arch.fpga13 years ago 7 replies

Because of the deficiencies in Verilog or the tools, I often have to write Perl to generate Verilog. Examples of these deficiencies...

Because of the deficiencies in Verilog or the tools, I often have to write Perl to generate Verilog. Examples of these deficiencies include: - Port list is not parameterizable without use of `defines - Many synthesizers don't understand preprocessing constant functions - Generate function in Verilog has limitations Rather than write Perl to generate Verilog modules, which is a cumbers...


Wow! No TestbenchWow!

Started by rickman in comp.arch.fpga7 years ago 11 replies

This is the first project I've done in Verilog in many years. With a long history in VHDL I have a new perspective and am seeing Verilog in a...

This is the first project I've done in Verilog in many years. With a long history in VHDL I have a new perspective and am seeing Verilog in a different way. I am finding some of the differences to be pretty interesting actually. I've already commented on the lack of the wildcard sensitivity only to find that VHDL has recently added this. Now I am learning how Verilog allows hierarchical...