Is Virtex-4 LX succesor for Spatan-3?

Started by Valeri Serebrianski in comp.arch.fpga13 years ago

In other words, are there any chances to meet with Spartan-4 (or kind of that) family in the future? It looks like Virtex-4 SX is successor for...

In other words, are there any chances to meet with Spartan-4 (or kind of that) family in the future? It looks like Virtex-4 SX is successor for Virtex-II and Virtex-4 FX - for Virtex-II Pro. Valeri


Virtex-4 5V tolerance

Started by Heiko Kalte in comp.arch.fpga12 years ago 4 replies

Hi, is there any difference between Virtex-II and Virtex-4 5V tolerence? I did not find any information about that. I want to connect 5V...

Hi, is there any difference between Virtex-II and Virtex-4 5V tolerence? I did not find any information about that. I want to connect 5V outputs to Virtex-4 inputs. I read all the articles about 174ohm resistors and QuickSwitch. Does all that apply to Virtex-4, too? Regards Heiko


Re: Amount of wire and logic

Started by Matthew Hicks in comp.arch.fpga10 years ago 5 replies

Old examples? I wonder what the breakdown is on the number of FPGAs you ship, Virtex-II Pro vs Virtex-4 vs Virtex-5. Since you aren't shipping...

Old examples? I wonder what the breakdown is on the number of FPGAs you ship, Virtex-II Pro vs Virtex-4 vs Virtex-5. Since you aren't shipping all the Virtex-5s yet, an I still can't find small unit quatities of Virtex-4s, I bet the Virtex-II Pro is still very relevant. ---Matthew Hicks > What do you want to achieve with these theoretical considerations? > As I said, routability


Remapping from Virtex-II to Virtex-4

Started by Lars in comp.arch.fpga12 years ago 5 replies

Anyone done any "what-if" remapping of Virtex-II designs to Virtex-4? I wanted to do this to see how the new technology performed, mainly to see...

Anyone done any "what-if" remapping of Virtex-II designs to Virtex-4? I wanted to do this to see how the new technology performed, mainly to see if it was worth the trouble to upgrade some existing designs. We did this quite successfully some years back, stepping from Virtex-E to Virtex-II. The main obstacle then was the new size Block RAM going from 4kbit to 18 kbit apiece. If we left our Un...


Virtex-5 clocking

Started by Saul Bernstein in comp.arch.fpga9 years ago 4 replies

Hi Folks, altough brand new I hope someone already made some experience with Virtex-5. I just switched from Virtex-4 to Virtex-5 and I...

Hi Folks, altough brand new I hope someone already made some experience with Virtex-5. I just switched from Virtex-4 to Virtex-5 and I must admit that the clock managment is... and remains... somewhat unclear to me! It's plain to see that the clock management is handled a bit differently than Virtex-4. Virtex-5 clocking uses both DCM (digital clock managers) technology for delay ...


Virtex-4 clocking

Started by Melanie Nasic in comp.arch.fpga12 years ago 5 replies

Hi fellow engineers, I am about to design a PCB containing a Xilinx Virtex-4 FPGA. I have some experience in board design and have already...

Hi fellow engineers, I am about to design a PCB containing a Xilinx Virtex-4 FPGA. I have some experience in board design and have already used several Virtex and Virtex-II devices. I want an ICS8442 LVDS clock synthesizer to be the clock source of my Virtex-4. A look at the Virtex-4 User Guide (ug070.pdf) scared me a lot by stating "Clock inputs can be configured for any I/O standard,...


virtex-4 power consumption

Started by sunr...@gmail.com in comp.arch.fpga10 years ago 1 reply

Now I have ported a design from virtex-2 to virtex-4,because the xilinx announced virtex-4 have a lower dynamic power,but actually when I...

Now I have ported a design from virtex-2 to virtex-4,because the xilinx announced virtex-4 have a lower dynamic power,but actually when I finished my design,running the same design with virtex-4,the metal face of the package is hot and this phenomenon is not existed in virtex-2.Why?Do anybody have the same phenomenon?


Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?

Started by azam in comp.arch.fpga12 years ago 2 replies

I was trying to determine the max frequency that can be clocked thru the Virtex-4 FPGA pins. While referring the Virtex-4 User Guide the (DC and...

I was trying to determine the max frequency that can be clocked thru the Virtex-4 FPGA pins. While referring the Virtex-4 User Guide the (DC and Switching characteristics) Section of the book has blank columns. Although the Virtex-4 FPGA Handbook mentions the capabiltiy to meet different I/O standards, I was wondering has anyone been able to exercise the I/Os of the Virtex Family above 300MHz...


Virtex 5 config Virtex 4

Started by maxascent in comp.arch.fpga8 years ago

I want to use a spi config mode for the Virtex 5 and then use a serial daisy chain to config a Virtex 4. Looking at the V5 user guide I am...

I want to use a spi config mode for the Virtex 5 and then use a serial daisy chain to config a Virtex 4. Looking at the V5 user guide I am pretty sure I can do this but could someone just confirm it? Thanks Jon


Do you like Virtex-5 ?

Started by Peter Alfke in comp.arch.fpga11 years ago 31 replies

Do you like Virtex-5 ? Then please vote for it... The editors of Electronic Design News think Virtex-5 is an innovative product; they have...

Do you like Virtex-5 ? Then please vote for it... The editors of Electronic Design News think Virtex-5 is an innovative product; they have nominated for their 17th Annual EDN Innovation Awards: the Xilinx Virtex-5 Design Team for "Innovator of the Year," and the Virtex-5 LXT platform for "Innovation of the Year" (in the Digital ICs category) EDN is asking their readers to select t...


Xilinx Virtex 4 Configuration Frames

Started by love...@gmail.com in comp.arch.fpga12 years ago

Hello All, I am looking at the reconfiguration capabilities of Virtex 4 devices. I have following questions related to Xilinx Virtex 4...

Hello All, I am looking at the reconfiguration capabilities of Virtex 4 devices. I have following questions related to Xilinx Virtex 4 configuration frames (frames here refer to the smallest addressable units in Virtex devices that can be reconfigured): a). What is the shape and size of a frame in Virtex 4 device? I know that in Virtex 2, each frame is one vertical column of the device. ...


FPGA Reconfiguration : Virtex-4 Frames

Started by Andreas Nett in comp.arch.fpga12 years ago 4 replies

Hello everybody, I'm working on dynamic partial reconfiguration of Xilinx Virtex-II FPGAs. In all Virtex-Device-Families the smallest...

Hello everybody, I'm working on dynamic partial reconfiguration of Xilinx Virtex-II FPGAs. In all Virtex-Device-Families the smallest (re-)configurable unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are running from the top of the device to the bottom. This means that during reconfiguration of a module in the center of the device, no signals can get from the left side to the...


Virtex-4 DCM CLKFX jitter

Started by RobJ in comp.arch.fpga12 years ago 2 replies

The data sheet refers you to the Xilinx web site, but I can't find anything there for Virtex-4. Does the Virtex-II CLKFX jitter calculator also...

The data sheet refers you to the Xilinx web site, but I can't find anything there for Virtex-4. Does the Virtex-II CLKFX jitter calculator also work for Virtex-4? Thanks, Rob


Fast Serial I/O on Virtex-5

Started by Anonymous in comp.arch.fpga11 years ago 5 replies

http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/index.htm Looking at Virtex-5 capabilities at Xilinx web...

http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/index.htm Looking at Virtex-5 capabilities at Xilinx web site I didn't find Rocket I/O. Is it gone? Why? Any hope for re-introduction in "Virtex-5 GX" ?


Virtex-4 Routing

Started by Miguel in comp.arch.fpga13 years ago 1 reply

Hi, I can't seem to find any documentation on Virtex-4 routing, no even a general schematic, i looked at the datasheets and user guides...

Hi, I can't seem to find any documentation on Virtex-4 routing, no even a general schematic, i looked at the datasheets and user guides but nothing. I saw a answer record that said that there weren't any TBUF's, and the data sheet shows that there is a switch matrix similar to Virtex-II in the CLB's. Does anyone have more information about it? is it similar to Virtex-II? When does Xilinx p...


About CLB inter-slice communication in Virtex

Started by null in comp.arch.fpga8 years ago 1 reply

In the Virtex 4 FPGA, slices within a CLB are interconnected with each other. However, in Virtex 5 and Virtex 6, there is no direct...

In the Virtex 4 FPGA, slices within a CLB are interconnected with each other. However, in Virtex 5 and Virtex 6, there is no direct connection between slices of a CLB. Why was this change made? Thanks --------------------------------------- Posted through http://www.FPGARelated.com


ISE6.1 : using virtex 800

Started by Dave Pedlow in comp.arch.fpga14 years ago 2 replies

I'm trying to create a bit file for a virtex xcv800 using ISE 6.1 but I can't select the virtex family. can I download it of the xilinx site...

I'm trying to create a bit file for a virtex xcv800 using ISE 6.1 but I can't select the virtex family. can I download it of the xilinx site somewhere? thanks DAve


help needed for Virtex-4

Started by saad in comp.arch.fpga9 years ago 1 reply

Hello All. Can anyone tell me the Push buttons ,leds names that i can write in the constraint file for Virtex -4. Any code that helps...

Hello All. Can anyone tell me the Push buttons ,leds names that i can write in the constraint file for Virtex -4. Any code that helps me test the functionality of virtex 4 will be appreciated.


GT10_PCI_EXPRESS_n

Started by Anonymous in comp.arch.fpga13 years ago 2 replies

According to the Xilinx documentation the GT10_PCI_EXPRESS_n primitive is only "supported for Virtex-II Pro X but not for Virtex-II...

According to the Xilinx documentation the GT10_PCI_EXPRESS_n primitive is only "supported for Virtex-II Pro X but not for Virtex-II or Virtex-II Pro". Does this mean that you can't use the Virtex-II Pro in a PCI-Express application? Is this related to the electrical idle, or are there other reasons? Thanks Petter -- A: Because it messes up the order in which people normally read tex...


Problem using virtex 4 and virtex 6 ibis models

Started by firefly in comp.arch.fpga5 years ago

I am facing some problems while using IBIS models in hyperlynx. I have to analyze a clock signal coming from 60MHz crystal oscillator and going...

I am facing some problems while using IBIS models in hyperlynx. I have to analyze a clock signal coming from 60MHz crystal oscillator and going to virtex 4 FPGA with part number (XC4VLX60-11FF1148) at pins AD17 and AE17 and then from vertix 4 the signal is going to Virtex 6 FPGA with part number (XC6VLX365T-FF1156) at pins G9 and H9. I downloaded IBIS models of virtex 4 and virtex 6 from the xili...