Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
Introduction This article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product....
Summary
This blog describes a practical FPGA technique to pack many asynchronous serial receivers into the area normally occupied by a single UART by leveraging LUT-based shift registers and other small-resource primitives. The author shows how to implement 16+ receivers with minimal logic, and discusses oversampling, timing, and vendor-specific implementation tips for common FPGA families.
Key Takeaways
- Use LUT-based shift registers (SRLs) and distributed RAM to implement compact serial receive pipelines
- Exploit carry chains and LUT packing to reduce per-line resource usage and fit many receivers in a small area
- Implement per-line oversampling and simple majority voting in hardware to reliably decode asynchronous serial data
- Optimize clocking and clock-domain crossing to maintain timing closure when replicating many receivers
Who Should Read This
FPGA designers (intermediate to advanced) implementing high-density asynchronous serial interfaces who need area-efficient multi-line UART solutions.
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