Summary

Glenn Kirilow's 2023 blog 'FPGA skills for the modern world' surveys contemporary FPGA toolchains and practical RTL skills, covering Verilog/SystemVerilog, VHDL, and High-Level Synthesis for DSP. It teaches pragmatic coding patterns, HLS trade-offs, and workflow steps to take designs from algorithm to Xilinx or Intel/Altera hardware.

Key Takeaways

• Understand when to choose Verilog/SystemVerilog vs VHDL and learn common synthesizable idioms for robust RTL.
• Apply High-Level Synthesis to prototype and accelerate FPGA-based DSP blocks, using HLS pragmas and performance trade-offs.
• Design synthesizable, testable RTL with recommended coding patterns and explicit clock-domain crossing handling.
• Optimize pipeline depth, resource use, and timing to meet constraints for Xilinx and Intel/Altera targets.

Who Should Read This

Intermediate FPGA and embedded engineers (or recent grads) who know basic digital design and want to update skills for modern FPGA toolchains, HLS, and DSP implementations.

Still RelevantIntermediate

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