Implementing video compression algorithms on reconfigurable devices

Stewart, Graeme

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The increasing density offered by Field Programmable Gate Arrays(FPGA), coupled with their short design cycle, has made them a popular choice for implementing a wide range of algorithms and complete systems. In this thesis the implementation of video compression algorithms on FPGAs is studied. Two areas are specifically focused on; the integration of a video encoder into a complete system and the power consumption of FPGA based video encoders. Two FPGA based video compression systems are described, one which targets surveillance applications and one which targets video conferencing applications. The FPGA video surveillance system makes use of a novel memory format to improve the efficiency with which input video sequences can be loaded over the system bus. The power consumption of a FPGA video encoder is analyzed. The results indicating that the motion estimation encoder stage requires the most power consumption. An algorithm, which reuses the intra prediction results generated during the encoding process, is then proposed to reduce the power consumed on an FPGA video encoder’s external memory bus. Finally, the power reduction algorithm is implemented within an FPGA video encoder. Results are given showing that, in addition to reducing power on the external memory bus, the algorithm also reduces power in the motion estimation stage of a FPGA based video encoder.

Summary

This 2010 thesis examines implementing video compression algorithms on FPGAs, focusing on system integration and power consumption of FPGA-based encoders. It presents two complete FPGA video compression systems (surveillance and conferencing) and practical techniques for memory formats, throughput, and low-power design.

Key Takeaways

Understand system-level integration challenges for FPGA video encoders, including bus interfaces and custom memory formats.
Apply a novel memory-formatting approach to improve throughput when loading video frames over system buses.
Estimate and reduce encoder power consumption through FPGA-aware architectural and implementation choices.
Design high-throughput, pipelined DSP modules (e.g., motion estimation and transform stages) optimized for FPGA resources.

Who Should Read This

Advanced FPGA/SoC designers and system architects aiming to build real-time, low-power FPGA-based video compression systems for applications like surveillance or videoconferencing.

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