VHDL syntheses timestamp

Hello all,

I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro).
Optimal would be someting like the 32Bit unix timestamp.

Does anybody know if there is some method to generate a timestamp during the "syntheses time" within 
vhdl?

Target system is xilinx spartan3 / xilinx web pack

regards
   Arne

On Sat, 21 Apr 2012 22:52:22 +0200, Arne Pagel wrote:

> Hello all,
> 
> I want to implement a "build" timestamp into some FPGA Designs (like the
> C __DATE__ makro).
> Optimal would be someting like the 32Bit unix timestamp.
> 
> Does anybody know if there is some method to generate a timestamp during
> the "syntheses time" within vhdl?
> 
> Target system is xilinx spartan3 / xilinx web pack
> 
> regards
>    Arne


I do the same thing in my projects here.

I also have constants for (an auto-incrementing) build number as well as 
a source code management system unique tag number.


The bad news is that this can't be done in native VHDL.

The good news is that it's trivial to do if you script your builds (i.e. 
you don't use an IDE (such as the ISE GUI) to build your designs).

Create a file with a package which contains the constants, e.g.


package foo is

  constant underscore_underscore_date : integer := 0;

end package foo;

package body foo is
end package body foo;


Modify your (probably TCL) build scripts to parse this file and call a 
program to patch in a new value for the constant before the file gets 
compiled.  Any scripting language would do; I use Perl for this.

The autoincrementing build number is a little more complicated - the 
script will check out the file; read the value of the constant; increment 
it then check the file back in.

Regards,
Allan

On 22/04/2012 04:28, Allan Herriman wrote:
> On Sat, 21 Apr 2012 22:52:22 +0200, Arne Pagel wrote:
>
>> Hello all,
>>
>> I want to implement a "build" timestamp into some FPGA Designs (like the
>> C __DATE__ makro).
>> Optimal would be someting like the 32Bit unix timestamp.
>>
>> Does anybody know if there is some method to generate a timestamp during
>> the "syntheses time" within vhdl?
>>
>> Target system is xilinx spartan3 / xilinx web pack
>>
>> regards
>>     Arne
>
>
> I do the same thing in my projects here.
>
> I also have constants for (an auto-incrementing) build number as well as
> a source code management system unique tag number.
>
>
> The bad news is that this can't be done in native VHDL.
>
> The good news is that it's trivial to do if you script your builds (i.e.
> you don't use an IDE (such as the ISE GUI) to build your designs).
..
>
>
> Modify your (probably TCL) build scripts to parse this file and call a
> program to patch in a new value for the constant before the file gets
> compiled.  Any scripting language would do;

Here is a very simple ready made Tcl one:

http://www.ht-lab.com/freeutils/date2hdl/date2hdl.html

Good luck,

Hans
www.ht-lab.com

thanks for you hint,

 > The bad news is that this can't be done in native VHDL.

I have suspected something like that.

 > Modify your (probably TCL) build scripts to parse this file and call a
 > program to patch in a new value for the constant before the file gets
 > compiled.  Any scripting language would do; I use Perl for this.

For my embedded C projects I do some similar stuff, I patch a version and date structure to the 
binary output after compiling.
So modifying a vhdl file with the needed information would not be the problem for me.
Currently I am still using the ISE GUI, but I couldn't find any option to run custom a pre-build 
command.
I am not sure that I am experienced enough with the build process to drop the GUI since I am using 
some IP cores and other GUI settings for my design.

Is there any option to use still the GUI but run some customized programs at some point?
Maybe be adding some lines to some tcl script somewhere?

On the other hand I would be very attractive to have more control over the vhdl build since I always 
have some problems determining the files which I should put under subversion revision control.

regards
   Arne

On Sunday, April 22, 2012 11:36:05 AM UTC+3, Arne Pagel wrote:
> thanks for you hint,
>=20
>  > The bad news is that this can't be done in native VHDL.
>=20
> I have suspected something like that.
>=20
>  > Modify your (probably TCL) build scripts to parse this file and call a
>  > program to patch in a new value for the constant before the file gets
>  > compiled.  Any scripting language would do; I use Perl for this.
>=20
> For my embedded C projects I do some similar stuff, I patch a version and=
 date structure to the=20
> binary output after compiling.
> So modifying a vhdl file with the needed information would not be the pro=
blem for me.
> Currently I am still using the ISE GUI, but I couldn't find any option to=
 run custom a pre-build=20
> command.
> I am not sure that I am experienced enough with the build process to drop=
 the GUI since I am using=20
> some IP cores and other GUI settings for my design.
>=20
> Is there any option to use still the GUI but run some customized programs=
 at some point?
> Maybe be adding some lines to some tcl script somewhere?
>=20
> On the other hand I would be very attractive to have more control over th=
e vhdl build since I always=20
> have some problems determining the files which I should put under subvers=
ion revision control.
>=20
> regards
>    Arne

In the past I did something similar (a date stamp not a time stamp) to this=
 but I was running it manually. I wrote a matlab code and I was running it =
with octave through a batch file via scheduled tasks, many times in a day. =
But later on I gave up using it because following a synthesis with date sta=
mp was not so good for me besides it was confusing. I went on with a manual=
 version and an automatic build number.=20

All levels of synthesis in ISE can be run with TCL scripts so instead of us=
ing ISE GUI you can run your synthesis with a script file, there are many t=
utorials for doing this.

Also in order to add a build number to your design simply you will write a =
function doing file read operation from a build file, increment it and writ=
e back again to that file and you will assign the return of the function (y=
our build number) to your signal like :=20

signal build_no : std_logic_vector(15 downto 0) :=3D MyBuildNumberFunction;

Assume that this assignment is done in a build.vhd file, at every synthesis=
 build no will increase.

On Sun, 22 Apr 2012 03:28:53 +0000, Allan Herriman wrote:

> On Sat, 21 Apr 2012 22:52:22 +0200, Arne Pagel wrote:
> 
>> Hello all,
>> 
>> I want to implement a "build" timestamp into some FPGA Designs (like
>> the C __DATE__ makro).
>> Optimal would be someting like the 32Bit unix timestamp.
>> 
>> Does anybody know if there is some method to generate a timestamp
>> during the "syntheses time" within vhdl?
>> 
>> Target system is xilinx spartan3 / xilinx web pack
>> 
>> regards
>>    Arne
> 
> 
> I do the same thing in my projects here.
> 
> I also have constants for (an auto-incrementing) build number as well as
> a source code management system unique tag number.
> 
> 
> The bad news is that this can't be done in native VHDL.
> 
> The good news is that it's trivial to do if you script your builds (i.e.
> you don't use an IDE (such as the ISE GUI) to build your designs).
> 
> Create a file with a package which contains the constants, e.g.
> 
> 
> package foo is
> 
>   constant underscore_underscore_date : integer := 0;
> 
> end package foo;
> 
> package body foo is end package body foo;
> 
> 
> Modify your (probably TCL) build scripts to parse this file and call a
> program to patch in a new value for the constant before the file gets
> compiled.  Any scripting language would do; I use Perl for this.
> 
> The autoincrementing build number is a little more complicated - the
> script will check out the file; read the value of the constant;
> increment it then check the file back in.


For completeness, I should probably point out that the other way of doing 
this involves getting the value of your constant from a top-level generic.
Many compilers (e.g. XST) allow the values of generics to be changed from 
the command line.

This still needs scripting if you want it to be automated.
Many IDEs will allow generic overrides through the GUI, but it is a 
manual process.

Regards,
Allan

On Sat, 21 Apr 2012 22:52:22 +0200
Arne Pagel <arne@pagelnet.de> wrote:

> Hello all,
> 
> I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro).
> Optimal would be someting like the 32Bit unix timestamp.
> 
> Does anybody know if there is some method to generate a timestamp during the "syntheses time" within 
> vhdl?
> 
> Target system is xilinx spartan3 / xilinx web pack
> 
> regards
>    Arne

I've needed to do this several times, and I agree with everyone else.
It can't be done in native VHDL, and probably can't be done through the
GUI.

For Altera, I've used Tcl to set generics in the build script.  For
Xilinx, I've used a Makefile to pass the result of $(date +s) as a
generic on the command line.  You can also use any scripting language
as a part of your build process to generate a package file.

Having tried all those approaches, they're all pains in the backside,
and none of them could I find a way to integrate into the GUI based
flow.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

On Sunday, April 22, 2012 2:09:44 AM UTC-7, Enes Erdin wrote:
> On Sunday, April 22, 2012 11:36:05 AM UTC+3, Arne Pagel wrote:
> > thanks for you hint,
> >=20
> >  > The bad news is that this can't be done in native VHDL.
> >=20
> > I have suspected something like that.
> >=20
> >  > Modify your (probably TCL) build scripts to parse this file and call=
 a
> >  > program to patch in a new value for the constant before the file get=
s
> >  > compiled.  Any scripting language would do; I use Perl for this.
> >=20
> > For my embedded C projects I do some similar stuff, I patch a version a=
nd date structure to the=20
> > binary output after compiling.
> > So modifying a vhdl file with the needed information would not be the p=
roblem for me.
> > Currently I am still using the ISE GUI, but I couldn't find any option =
to run custom a pre-build=20
> > command.
> > I am not sure that I am experienced enough with the build process to dr=
op the GUI since I am using=20
> > some IP cores and other GUI settings for my design.
> >=20
> > Is there any option to use still the GUI but run some customized progra=
ms at some point?
> > Maybe be adding some lines to some tcl script somewhere?
> >=20
> > On the other hand I would be very attractive to have more control over =
the vhdl build since I always=20
> > have some problems determining the files which I should put under subve=
rsion revision control.
> >=20
> > regards
> >    Arne
>=20
> In the past I did something similar (a date stamp not a time stamp) to th=
is but I was running it manually. I wrote a matlab code and I was running i=
t with octave through a batch file via scheduled tasks, many times in a day=
. But later on I gave up using it because following a synthesis with date s=
tamp was not so good for me besides it was confusing. I went on with a manu=
al version and an automatic build number.=20
>=20
> All levels of synthesis in ISE can be run with TCL scripts so instead of =
using ISE GUI you can run your synthesis with a script file, there are many=
 tutorials for doing this.
>=20
> Also in order to add a build number to your design simply you will write =
a function doing file read operation from a build file, increment it and wr=
ite back again to that file and you will assign the return of the function =
(your build number) to your signal like :=20
>=20
> signal build_no : std_logic_vector(15 downto 0) :=3D MyBuildNumberFunctio=
n;
>=20
> Assume that this assignment is done in a build.vhd file, at every synthes=
is build no will increase.

I use a Perl script to update a Verilog parameter.  You could do a similar =
thing with VHDL.  I manually run the script when I want to embed the curren=
t Unix data/time value.

It's not automated, but it does the job for me.

John P

This is a good thread.

In out system, the application software would check a version number
register at boot time to make sure it was running with the right FPGA
design.  The problem with my manually updated version register is that I
always forgot to update it until after the FPGA build and test work was
done.  To update the version number I had to re-run the FPGA build and, of
course, the testing.

Our FPGA had a PCIe interface so it must configure from an on-board flash
in order to boot in time for PCIe enumeration cycles.  The on-board
configuration flash is readable and writeable across the PCIe bus by the
Linux host. Eventually, I noticed that the Xilinx configuration bit file
header contains a date and time that is automatically incremented at build
time.  

I tried to get the software guys to just read the bit file header and parse
the date and time out of there.  They could have just used those fields as
a unique identifier.  In the end, I could never convince them to do that.

I have actually, sent suggestions to Xilinx on this subject but I haven't
heard of any enhancements to support an automatically updated version or
date/time register in the code.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

padudle <93037@embeddedrelated> wrote:
 
> In out system, the application software would check a version number
> register at boot time to make sure it was running with the right FPGA
> design.  The problem with my manually updated version register is that I
> always forgot to update it until after the FPGA build and test work was
> done.  To update the version number I had to re-run the FPGA build and, of
> course, the testing.
 
If you use a version control systems, such as CVS, SVN, 
(and I believe also GIT) there is a way to have it automatically 
update a field in the file as it is checked in with the version
number. You should be able to use that to make a hardware readable
register with the version number in it.

-- glen