Virtex 4 Cameralink DCM Limitation

On Jun 20, 7:08=A0pm, carlton...@gmail.com wrote:
> Lasse,
>
> The preferred way to do the clock derivation would be as Gabor suggests, =
use a PLL. Unfortunately for the OP, V4 only has DCMs.
>
> The reason for the 2 cascaded DCMs is because the OP has a desired clock =
relationship which is out of bounds for a single DCM. The OP's desired link=
 clock frequency is something less than 32MHz. Which means that the first D=
CM
> needs to be a maximum range setup DCM. Problem is, the maximum range DCM =
cannot directly derive a 3.5x or 7x clock based upon the limited input cloc=
k frequency. So for the first DCM, the clk2x output is used to double the
> frequency of the link clock frequency.
>
> The clk2x clock frequency is now of a value whereby a maximum frequency s=
etup DCM can be used to derive the overall 3.5x or 7x clock by using the cl=
kfx and setting M and D to values which provide the overall desired frequen=
cy.
>
> As far as phase relationship on this second DCM, if clk0 is piped back to=
 clkfb, clkfx is supposed to be aligned to the clk0 but with the twist that=
 it is every D clkin cycles. If clk0 is aligned to clkin, clkfx should also=
 be aligned to clkin.
>
> Gabor is right, that depending upon arrangement of the 2 cascaded DCMs it=
 is possible that the jitter can be out of limits. Generally speaking, it i=
s when clkfx is cascaded or clkfx is part of the feedback path where proble=
ms can begin to arise. I believe however that the above implementation is o=
k with respect to jitter being within limits because clkfx is only used
> as a final output and is not being fed back into the cascaded DCMs.
>
> Regards,
> Carlton

by why not just use the clk fx directly? as far as I can tell it can
do 7x

might even go crazy and try 14x and use both edges via input ddr
flops, that way
you get 4x data rate sampling and realign at every edge which is how
most full-speed
usb devices do it

-Lasse

Hi Lasse,

The problem is that the OP desires an incoming frequency less than 32MHz.
This means the maximum-range type of DCM has to be used in order to accept =
the less than 32MHz clock input. The tradeoff is that the clkfx is restrict=
ed to what frequencies can be generated. In this case the upper limit on cl=
kfx is < 3.5x and also 7x for a maximum-range type DCM.

To illustrate the limit, try creating a DCM which uses the clkfx in the cor=
e generator for a V-4 target. Use an input frequency < 32MHz.


Regards,
Carlton