fifo or sdram bug?

Fifo or SDRAM?

It turned out to be the fifo. Data captured directly from fifo
input/output showed that the problem is from the suspected fifo. It must
be some sort of fifo ip internal failure of obscure nature. The issue also
disappeared by reseting this fifo (using dedicated reset that does not
reset anything else). The chosen remedy is to apply this reset immediately
before any capture rather than redsign a fifo.

There are many fifos in our design but only this one showed failure.

Thanks for all your contributions.

Kaz 

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