Quartus, building "Safe" FMSs

I tried to contact Altera's upport on Safe FSMs and had to explain
what can cause a FSM to get lost and about recovery.  We even talked a
bit about how some of the other tools like Synplicity handle this. 
This was Altera's responce:


>Description: 	want to code a state machine and if it goes into an
undefined >state, what does he need to code to reset the state machine

>Unfotunately, it is not our duty to tell you or teach you how to code
in vhdl. >However, there are guidlines and references that you may
refer to from our web >site and in the Quartus II Help. To do so, you
may simply do a search on our >site or use the key phrase "state
machine" in the Quartus II Help.
>
>Regards,


What is interesting is that they never mention "Safe" in the orignal
question. I had spent a lot of time looking for the information on
their site but turned up nothing.

With Altera's support once again being a dead end, does anyone know if
there is a switch for this in Quartus, like Synplify and other tools? 
If not, has anyone dug into what it takes to make the tools create the
added logic?

I wonder if using the "minimal" gate feature and define a 2^nth FSM,
then encode all of the states if it would optimize out states that
have no entry point or not.  Maybe there is a switch for the optimizer
as well?   I don't want to waste a lot of time trying things to find a
method that works.

lecroy wrote:

>>Description:  want to code a state machine and if it goes into an
> undefined >state, what does he need to code to reset the state machine

> I wonder if using the "minimal" gate feature and define a 2^nth FSM,
> then encode all of the states if it would optimize out states that
> have no entry point or not.  Maybe there is a switch for the optimizer
> as well?   I don't want to waste a lot of time trying things to find a
> method that works.

This has been discussed at great length on comp.lang.vhdl:
http://groups.google.com/groups?q=safe+state+machine+vhdl

There's no simple answer. 
Consider using the binary (minimal bits) setting
and see what you get.

  -- Mike Treseler

> This has been discussed at great length on comp.lang.vhdl:
> http://groups.google.com/groups?q=safe+state+machine+vhdl
> 
> There's no simple answer. 
> Consider using the binary (minimal bits) setting
> and see what you get.
> 
>   -- Mike Treseler

Mike,

Thanks.  I will read the thread. It always seems to be a problem when
I try a new tool. And your right, it is not a simple problem when the
people developing the tools have not considered the problem. I would
have thought the Quartus tool would have had this covered.  I like
using the Synplify tools for this reason.

I had reposted the question to Altera last week but have yet to hear a
responce.  If anything comes of it I will post.

Synplify has two different "safe" modes.

One is to prevent sequential optimizations on the state
register.   You do this with the syn_preserve attribute
on the register (not the best name - I know).  Most
synthesis tools have some way to do this.

The second is to let Synplify extract the state machine
and to specify a syn_encoding attribute of "safe,onehot"
or "safe,sequential" on the state register.   In this case
Synplify automatically builds an extra reset condition
based on a pipelined detection of an illegal state.  By
separating the illegal state detection logic and giving
ourselves more time to detect the illegal states we can
make a more area efficient recovery circuit and a faster FSM.
This feature is covered by a patent so you probably won't
see it in other tools.

- Ken McElvain

lecroy wrote:

>>This has been discussed at great length on comp.lang.vhdl:
>>http://groups.google.com/groups?q=safe+state+machine+vhdl
>>
>>There's no simple answer. 
>>Consider using the binary (minimal bits) setting
>>and see what you get.
>>
>>  -- Mike Treseler
> 
> 
> Mike,
> 
> Thanks.  I will read the thread. It always seems to be a problem when
> I try a new tool. And your right, it is not a simple problem when the
> people developing the tools have not considered the problem. I would
> have thought the Quartus tool would have had this covered.  I like
> using the Synplify tools for this reason.
> 
> I had reposted the question to Altera last week but have yet to hear a
> responce.  If anything comes of it I will post.