Forums

Altera HSMC connector

Started by Rick C. Hodgin April 5, 2016
Hello all.  I'm looking for some information about Altera's FPGA.  I have
this Cyclone V GX dev board:

    https://www.altera.com/products/boards_and_kits/dev-kits/partners/kit-terasic-cyclone-v-gx-starter.html

It has a 160-pin HSMC connector, which connects using this flexible cable:

    https://www.altera.com/en_US/pdfs/literature/ds/hsmc_spec.pdf
    http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=275

I'm wondering if this connector can be used for general purpose off-board
communication for custom uses outside of connecting to other Mezzanine
boards?  Could I, for example, connect some wires to the pins and signal
them independently for GPIO?

Or... is this cable interface something proprietary that only allows
interconnect between Mezzanine devices?

Best regards,
Rick C. Hodgin
Rick C. Hodgin wrote:

> Hello all. I'm looking for some information about Altera's FPGA. I have > this Cyclone V GX dev board: > > https://www.altera.com/products/boards_and_kits/dev-kits/partners/kit-terasic-cyclone-v-gx-starter.html > > It has a 160-pin HSMC connector, which connects using this flexible cable: > > https://www.altera.com/en_US/pdfs/literature/ds/hsmc_spec.pdf > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=275 > > I'm wondering if this connector can be used for general purpose off-board > communication for custom uses outside of connecting to other Mezzanine > boards? Could I, for example, connect some wires to the pins and signal > them independently for GPIO? > > Or... is this cable interface something proprietary that only allows > interconnect between Mezzanine devices? > > Best regards, > Rick C. Hodgin
It's a bit of a pain as connectors go. http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=67&No=322&PartNo=1 makes a convenient breakout. You want the (M), to mate the dev kit, not the (F). -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.
On Tuesday, April 5, 2016 at 2:53:15 PM UTC-4, Rob Gaddi wrote:
> Rick C. Hodgin wrote: > > Hello all. I'm looking for some information about Altera's FPGA. I have > > this Cyclone V GX dev board: > > > > https://www.altera.com/products/boards_and_kits/dev-kits/partners/kit-terasic-cyclone-v-gx-starter.html > > > > It has a 160-pin HSMC connector, which connects using this flexible cable: > > > > https://www.altera.com/en_US/pdfs/literature/ds/hsmc_spec.pdf > > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=275 > > > > I'm wondering if this connector can be used for general purpose off-board > > communication for custom uses outside of connecting to other Mezzanine > > boards? Could I, for example, connect some wires to the pins and signal > > them independently for GPIO? > > > > Or... is this cable interface something proprietary that only allows > > interconnect between Mezzanine devices? > > It's a bit of a pain as connectors go. > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=67&No=322&PartNo=1 makes a convenient breakout. You want the (M), to mate the dev kit, not the (F). > > -- > Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Thank you, Rob. That's exactly what I was looking for. Best regards, Rick C. Hodgin
On Tuesday, April 5, 2016 at 3:03:53 PM UTC-4, Rick C. Hodgin wrote:
> On Tuesday, April 5, 2016 at 2:53:15 PM UTC-4, Rob Gaddi wrote: > > Rick C. Hodgin wrote: > > > Hello all. I'm looking for some information about Altera's FPGA. I have > > > this Cyclone V GX dev board: > > > > > > https://www.altera.com/products/boards_and_kits/dev-kits/partners/kit-terasic-cyclone-v-gx-starter.html > > > > > > It has a 160-pin HSMC connector, which connects using this flexible cable: > > > > > > https://www.altera.com/en_US/pdfs/literature/ds/hsmc_spec.pdf > > > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=275 > > > > > > I'm wondering if this connector can be used for general purpose off-board > > > communication for custom uses outside of connecting to other Mezzanine > > > boards? Could I, for example, connect some wires to the pins and signal > > > them independently for GPIO? > > > > > > Or... is this cable interface something proprietary that only allows > > > interconnect between Mezzanine devices? > > > > It's a bit of a pain as connectors go. > > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=67&No=322&PartNo=1 makes a convenient breakout. You want the (M), to mate the dev kit, not the (F). > > > > -- > > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > > Thank you, Rob. That's exactly what I was looking for.
Ordered. Thank you again. Best regards, Rick C. Hodgin
On 4/5/2016 3:23 PM, Rick C. Hodgin wrote:
> On Tuesday, April 5, 2016 at 3:03:53 PM UTC-4, Rick C. Hodgin wrote: >> On Tuesday, April 5, 2016 at 2:53:15 PM UTC-4, Rob Gaddi wrote: >>> Rick C. Hodgin wrote: >>>> Hello all. I'm looking for some information about Altera's FPGA. I have >>>> this Cyclone V GX dev board: >>>> >>>> https://www.altera.com/products/boards_and_kits/dev-kits/partners/kit-terasic-cyclone-v-gx-starter.html >>>> >>>> It has a 160-pin HSMC connector, which connects using this flexible cable: >>>> >>>> https://www.altera.com/en_US/pdfs/literature/ds/hsmc_spec.pdf >>>> http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=275 >>>> >>>> I'm wondering if this connector can be used for general purpose off-board >>>> communication for custom uses outside of connecting to other Mezzanine >>>> boards? Could I, for example, connect some wires to the pins and signal >>>> them independently for GPIO? >>>> >>>> Or... is this cable interface something proprietary that only allows >>>> interconnect between Mezzanine devices? >>> >>> It's a bit of a pain as connectors go. >>> http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=67&No=322&PartNo=1 makes a convenient breakout. You want the (M), to mate the dev kit, not the (F). >>> >>> -- >>> Rob Gaddi, Highland Technology -- www.highlandtechnology.com >> >> Thank you, Rob. That's exactly what I was looking for. > > Ordered. Thank you again.
I think you are better off not using the FPGA eval board and just making your own board with the 386 and the FPGA. The adapters and cables are going to add a lot of capacitance and noise to your signals. Why mess with the added complexity? -- Rick
Rick C. Hodgin wrote:
> Rick C. Hodgin wrote: > > Rob Gaddi wrote: > > > It's a bit of a pain as connectors go. > > > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language= English&CategoryNo=67&No=322&PartNo=1 > > > makes a convenient breakout. You want the (M), to mate the dev kit, not the (F). > > > > > > -- > > > Rob Gaddi, Highland Technology > > > www.highlandtechnology.com > > > > Thank you, Rob. That's exactly what I was looking for. > Ordered. Thank you again.
Received. Fits the board like it was made for it. :-) Best regards, Rick C. Hodgin
rickman wrote:
> I think you are better off not using the FPGA eval board and just > making your own board with the 386 and the FPGA. The adapters > and cables are going to add a lot of capacitance and noise > to your signals. Why mess with the added complexity?
I'll need enough capacity to simulate my ISA, as well as drive the Am386. They will more or less execute together, with off-device debugging signals to control operations. Would the capacitance be an issue at a few hundred KHz max? I plan to make the custom Am386 plug straight in to the three GPIO ports. Best regards, Rick C. Hodgin
On Mon, 11 Apr 2016 11:12:04 -0700, Rick C. Hodgin wrote:

> rickman wrote: >> I think you are better off not using the FPGA eval board and just >> making your own board with the 386 and the FPGA. The adapters and >> cables are going to add a lot of capacitance and noise to your signals. >> Why mess with the added complexity? > > I'll need enough capacity to simulate my ISA, as well as drive the > Am386. They will more or less execute together, with off-device > debugging signals to control operations. > > Would the capacitance be an issue at a few hundred KHz max? I plan to > make the custom Am386 plug straight in to the three GPIO ports. > > Best regards, > Rick C. Hodgin
You may need to slow down the Cyclone IO edges. If memory serves the V has sub ns rise times. Your cable and 386 input cap will help limit that some. Of course pay close attention to the setup and hold times the 386 is going to require. At one time PLX had local bus to pci chips. I have not checked on them lately. They got bought by Avago some time back. They may only do PCIe now. -- Chisolm Republic of Texas
Rick C. Hodgin wrote:

> Rick C. Hodgin wrote: >> Rick C. Hodgin wrote: >> > Rob Gaddi wrote: >> > > It's a bit of a pain as connectors go. >> > > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language= English&CategoryNo=67&No=322&PartNo=1 >> > > makes a convenient breakout. You want the (M), to mate the dev kit, not the (F). >> > > >> > > -- >> > > Rob Gaddi, Highland Technology >> > > www.highlandtechnology.com >> > >> > Thank you, Rob. That's exactly what I was looking for. >> Ordered. Thank you again. > > Received. Fits the board like it was made for it. :-) > > Best regards, > Rick C. Hodgin
I'm glad all the research effort I put in of looking over at the stack of same sitting on the corner of my desk and writing down the number from the box came in handy. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.
On 4/11/2016 2:12 PM, Rick C. Hodgin wrote:
> rickman wrote: >> I think you are better off not using the FPGA eval board and just >> making your own board with the 386 and the FPGA. The adapters >> and cables are going to add a lot of capacitance and noise >> to your signals. Why mess with the added complexity? > > I'll need enough capacity to simulate my ISA, as well as drive the Am386. They will more or less execute together, with off-device debugging signals to control operations. > > Would the capacitance be an issue at a few hundred KHz max? I plan to make the custom Am386 plug straight in to the three GPIO ports.
You won't have trouble with lines that are essentially data lines, you don't care if they ring. The trouble will be with clock like lines. That will include the actual clock and potentially the read/write strobes depending on how you implement the interface circuit. More importantly, you may have trouble with ground bounce. I've put my scope on the far end of disk drive ribbon cables before and the noise on the ground can be horrendous. The issue is not the clock rate, it is the edge rate. You can configure the FPGA for slower edge rates, but you can't do anything about the 386 edge rates. Running 100+ signal lines over a ribbon cable is just not a good idea unless you use differential signalling. You may get away with it, you may not. Since you are building a custom board anyway, why not just include the FPGA? The other way to do this is to use a set of bidirectional latches/buffers and let the FPGA access the interface via a simple serial interface using LVDS signalling. The FPGA already includes this functionallity. You just need to add a few interface chips to the 386 board along with your quickswitch devices. -- Rick