VHDL Editors (esp. V3S)

thomas.entner99@gmail.com wrote:
> As X and A's integrated editors are more or less limited, I guess many people will looking for better alternatives.
> 
> The usual suspects will be Emacs (with VHDL mode) and Sigasi.
> 
> For me personally, I never really liked Emacs and found Sigasi just a bit too expensive.
> 
> So some time ago I came across V3S from www.vide-software.at. It is a quite powerful and fair priced VHDL plug-in for Visual Studio (Stand-alone version with Visual Studio redistributable package also available). I could also watch the progress over the last few months and I really like it.
> 
> The only drawback is the missing Linux support. However, there appears to be a Linux version of "Visual Studio Code". I have not checked yet if this works together with the plug-in. Maybe someone else has?
> 
> Regards,
> 
> Thomas
> 
> P.S.: I am in no way related to V3S, just a happy user. I want to sell you EEBlasters, JPEG encoders and cameras at www.entner-electronics.com, however ;-)

   I do almost all of my work in Verilog, but I do have comments
about editors in general.

   I gave up on using Xilinx built-in editors after the first major
update.  For no apparent reason, they completely changed the user
interface.  Im my opinion, the best editor is the one you're most
familiar with.  You spend a lot of time discovering the easiest way
to do each editing task.  So it makes no sense to depend on an
editor that changes everything you've learned with each major
software update.

   I've been using Med for some time now.  Unfortunately it doesn't
seem to be maintained anymore, but I'm happy with the functionality
of the old version I'm using.  It didn't come with a Verilog language
template, but gave me the option of making my own.  It has some
interesting capabilities like column-selection and paste being
separate things.  That is, regardless of how you copy or cut a
piece of text, it can be pasted as a column (rectangular selection)
or normally.  So you can copy a rectangular selection and paste it
in line, or vice versa.  Indenting is rather crude, but good enough
for my work.

   I actually tried Sigasi's editor briefly, but found it lacking some
of the features I was used to, and I wasn't so interested in the
project management portion since I generally work from the Xilinx
GUI.  At this point, I'm not sure which feature I missed, since it's
been a while since I tried it.  What I was hoping to find (in any
editor) was the ability to automatically re-indent code based on
the language structure.  This is something that has been in C
editors for a long time.  I seem to recall the operation called
"prettify," as in to make the source look pretty.  I like my code
in a particular indenting style, and find it easier to read other
peoples code after I've re-styled it to match my preferences.

-- 
Gabor

>    I do almost all of my work in Verilog, but I do have comments
> about editors in general.
> 
>    I actually tried Sigasi's editor briefly, but found it lacking some
> of the features I was used to, and I wasn't so interested in the
> project management portion since I generally work from the Xilinx
> GUI.  

The last time I checked, both Sigasi and V3S had quite limited Verilog support, I think in the moment they are really VHDL editors, with some basic Verilog support if you need to edit a Verilog file here and then...

I did a Verilog project only once, about 2 years ago, and at that time VEditor worked the best for me by far, at least from the free options (it was also recommended to me by the respective customer, but I first tried some different approaches). It flagged a lot of issues in the source code that are not detected by a Verilog compiler and saved me a lot of time looking for stupid bugs. (In contrast, VHDL editors flag errors, that would be detected by the compiler... But this is a different topic ;-)

Regards,

Thomas

www.entner-electronics.com - Home of EEBlaster and JPEG Codec

I have installed V3S ...

When I instantiate a component in the following manner:

i_my: entity work.sub

V3S complains that sub is unknown ...

How can I suppress that behavior? (Ok, apart from using a component declaration...)

Noro

Am Donnerstag, 2. Februar 2017 09:36:34 UTC+1 schrieb noreeli....@gmail.com:
> I have installed V3S ...
> 
> When I instantiate a component in the following manner:
> 
> i_my: entity work.sub
> 
> V3S complains that sub is unknown ...
> 
> How can I suppress that behavior? (Ok, apart from using a component declaration...)
> 
> Noro

<sub> must be defined somewhere in the project (either another entity, or in a library/package) -> add that file to the project

Thomas