Article about using Non-Project Mode

Started by Ilya Kalistru June 2, 2017
Hi!
During the discussion about "Test Driven Design?" I promised to write a paper about
Non-Project Mode and how it helps with testing.
The problem is that I have never written any article. Moreover, English is not my
native language.
I kindly ask you to review the article and help me to improve it. It is in Google
docs and leaving comments right in the document is allowed. You also can comment it
here if it is more convenient for you.
Thanks.

https://docs.google.com/document/d/17LgQjxYdh8Dxy4NdFWWNYQ7up8MFNG4GQdPfv3s5LzI/edit?usp=sharing
To comment a phrase in the document, you just select it and click "comment icon"
which appears at the end if the line.
On Friday, June 2, 2017 at 4:55:42 PM UTC-6, Ilya Kalistru wrote:
> Hi! > During the discussion about "Test Driven Design?" I promised to write a paper
about Non-Project Mode and how it helps with testing.
> The problem is that I have never written any article. Moreover, English is not my
native language.
> I kindly ask you to review the article and help me to improve it. It is in Google
docs and leaving comments right in the document is allowed. You also can comment it here if it is more convenient for you.
> Thanks. > >
https://docs.google.com/document/d/17LgQjxYdh8Dxy4NdFWWNYQ7up8MFNG4GQdPfv3s5LzI/edit?usp=sharing Thanks. I'm in the sim phase on my project right now but when I get back into PAR I'm going to check this out.
On Saturday, June 10, 2017 at 11:42:47 PM UTC+3, Kevin Neilson wrote:
> On Friday, June 2, 2017 at 4:55:42 PM UTC-6, Ilya Kalistru wrote: > > Hi! > > During the discussion about "Test Driven Design?" I promised to write a paper
about Non-Project Mode and how it helps with testing.
> > The problem is that I have never written any article. Moreover, English is not
my native language.
> > I kindly ask you to review the article and help me to improve it. It is in
Google docs and leaving comments right in the document is allowed. You also can comment it here if it is more convenient for you.
> > Thanks. > > > >
https://docs.google.com/document/d/17LgQjxYdh8Dxy4NdFWWNYQ7up8MFNG4GQdPfv3s5LzI/edit?usp=sharing
> > Thanks. I'm in the sim phase on my project right now but when I get back into PAR
I'm going to check this out. I have closed access to the draft of the article because I shared it for some time just to get some reviews and suggestions. I'll publish the article as soon as it is reviewed by my employer. Kevin, if you have an Google account you can request access to the draft and I'll grant it to you.
Ilya Kalistru <stebanoid@gmail.com> wrote:
> I have closed access to the draft of the article because I shared it > for some time just to get some reviews and suggestions.
It looked fine to me. It did suffer slightly from falling into the strangely common trap of assuming FPGA=Xilinx, so maybe that should be signposted up front a bit more. (It's possible to do similar things with Altera but I think the article would need too much restructuring to account for different ways of doing things. I'm not familiar enough with Lattice or Microsemi to comment on those toolchains) Theo
On Monday, 12 June 2017 13:02:54 UTC+3, Theo Markettos  wrote:

> It looked fine to me. It did suffer slightly from falling into the > strangely common trap of assuming FPGA=3DXilinx, so maybe that should be > signposted up front a bit more. >=20 > (It's possible to do similar things with Altera but I think the article > would need too much restructuring to account for different ways of doing > things. I'm not familiar enough with Lattice or Microsemi to comment on > those toolchains) >=20 > Theo
Thank you for your response. On one hand, I tried not to make the article too Xilinx-specific because I = believe that other tool chains have the same problems and that they likely = to have similar modes of operation. On the other hand, I do not have non-Xi= linx experience to make any specific advice for other toolchains. I see tha= t I need to rework the beginning of the paper to make it clear.
On 06/12/2017 10:40 AM, Ilya Kalistru wrote:
> On Monday, 12 June 2017 13:02:54 UTC+3, Theo Markettos wrote: > >> It looked fine to me. It did suffer slightly from falling into the >> strangely common trap of assuming FPGA=Xilinx, so maybe that should be >> signposted up front a bit more. >> >> (It's possible to do similar things with Altera but I think the article >> would need too much restructuring to account for different ways of doing >> things. I'm not familiar enough with Lattice or Microsemi to comment on >> those toolchains) >> >> Theo > > Thank you for your response. > > On one hand, I tried not to make the article too Xilinx-specific because I believe
that other tool chains have the same problems and that they likely to have similar modes of operation. On the other hand, I do not have non-Xilinx experience to make any specific advice for other toolchains. I see that I need to rework the beginning of the paper to make it clear.
>
I'd avoid trying to be too generic. I've set up Makefile based flows under both Xilinx (ISE) and Altera Quartus and they have nothing to do with one another. Totally different paradigms, problems, syntaxes, etc. As near as I was able to tell while you had that document publicly available, you're trying to describe how to a non-project flow under Vivado at this current point in time. That's valuable and helpful. If you haven't made it public again about a month from how I'll probably start harassing you for a copy by email. Better to do that well than to half-ass a generic document that almost by definition can't be right. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.
I need to accomplish several formal steps before publishing it.
It uses some code I've written on my workplace and, therefore, I must obey corporate
rules of publishing articles. As soon as I get the article reviewed by my boss and
colleagues, I'll try to publish it on fpgarelated.com and may be somewhere else.
> I'll publish the article as soon as it is reviewed by my employer. > > Kevin, if you have an Google account you can request access to the draft and I'll
grant it to you. Ilya, Thanks for the document. You inspired me to use non-project mode and now that I have a script for one of my projects I can just keep reusing it. The only thing I'd say about your document is that I think it had some Windows-specific stuff which wasn't obvious to me at first. There is also a brief intro to non-project mode in the Vivado Quick Reference: http://tinyurl.com/yb9d8y8d
On Saturday, July 1, 2017 at 12:15:38 AM UTC+3, Kevin Neilson wrote:
> > I'll publish the article as soon as it is reviewed by my employer. > > > > Kevin, if you have an Google account you can request access to the draft and
I'll grant it to you.
> > Ilya, > Thanks for the document. You inspired me to use non-project mode and now that I
have a script for one of my projects I can just keep reusing it. The only thing I'd say about your document is that I think it had some Windows-specific stuff which wasn't obvious to me at first.
> > There is also a brief intro to non-project mode in the Vivado Quick Reference: > > http://tinyurl.com/yb9d8y8d
It's finally published on edn.com ! http://tinyurl.com/y9ekp7lf Thanks a lot to anyone who have helped me to improve the article. Kevin, I'm so glad that I inspired you! In fact, it was a goal of the article to encourage more people to use this mode, so that IDE developers pay more attention to this way of managing projects. I hope that some inconvenience of using IPs in this mode will not discourage you. :) I am planning to write another article devoted to this problem. I hope I will find time for doing some research on this matter and for writing article.