LVDS through connectors

James Morrison wrote:
> On Thu, 2005-01-20 at 05:00 -0800, Marc Randolph wrote:
> 
> 
>>I was figuring that someone would disagree with what I said - I just
>>didn't figure it would be within a half hour!
> 
> 
> Life is all about timing!
> 
> 
>>I was actually referring to the whole solution when I was referring to
>>the speed: signalling type (LVDS, which has slower edges than PECL and
>>CML), termination location (hopefully on-chip), voltage swing, etc.
> 
> 
> I don't disagree with what you've said and appreciate the insight from
> your past experience.  I guess what I was reacting to is the concept
> that the connector doesn't matter.  It does matter, but as I said, it
> all depends on how much margin you have in your design.  In a particular
> design it may or may not matter based on a hundred other factors.
> 
> As you mentioned, in a lot of ways differential signalling is a whole
> lot easier to deal with.  Of course there is no such thing as a
> single-ended signal.  Ground is typically the other end that happens to
> be common among all signals.

Thanks for the replies, they really help me get a better picture! I 
don't have TigerSHARCs, just two Spartan-3 FPGAs.

I wonder what is the acceptable mismatch between the traces of an LVDS 
pair? Given ~6 in/ns propagation speed and, let's say 0.2 ns rise time, 
the rise time length is 1.2 inches. Is something like 10% of that, or 
120 mils, acceptable trace length mismatch? I think it will be even 
lower than that when the final routing of the board is done.

Any thoughs about vias on the signal traces?

Thanks again,
-- Georgi

Mark Smith wrote:
> Hi Georgi,
> 
> For Higher speeds, I would recommend the AMP Mictor connectors.
> 
> This document is a useful design guide:
> 
> http://www.latticesemi.com/lit/docs/technotes/tn1033.pdf
> Regards
> 
> Mark Smith
> Strategic Marketing
> Lattice Semiconductor

That's great, thanks!

-- Georgi

On 19 Jan 2005 17:29:13 -0800, "Marc Randolph" <mrand@my-deja.com>
wrote:

>Georgi Beloev wrote:
>> Hi all,
>>
>> I'm designing a system in which a 4-bit + clock LVDS point-to-point
>bus
>> has to connect two FPGAs. The two FPGAs are on two different
>boards--one
>> is on a mainboard and the other is on a plug-in board.
>>
>> What kind of board-to-board connector is recommended for high-speed
>> (~400 Mbps) LVDS signals? Connector parameters to look for? Signal
>> integrity issues? Board layout with regard to the connectors? Rules
>of
>> thumb?
>
>Howdy Georgi,
>
>I hate to say that it doesn't matter, but in the grand scheme of
>things, the type or style of the connector is not of huge importance at
>that speed, as long as one pin isn't massively longer than another
>(which occurs with some types of right angle connectors).  We run many
>times that speed using the worst connector you can imagine.
>
>Much more important is the stuff that Brad mentioned: keep _p/_n pair
>trace length the same and routed as a diff pair into and out of the
>connector - and routed against a ground plane if possible.  Give
>yourself a ground pin next to each pair within the connector.
>Have fun,
>
>   Marc

I'll mostly agree with you.  We are running three LVDS pairs (200MHz)
plus power over standard 6' shielded Cat5 patch cords with RJ45 jacks
at each end.  We were very careful with the PCB layouts to run the
pairs together, to match the lengths, and to avoid vias.  Works fine.

BTW, we use the common-mode filter termination (see figure 3.3 in the
National Semiconductor LVDS Owner's Manual).

================================

Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com