Very Stupid XST verilog synthesis question...

OK.  I'm just braindead, my verilog is horribly rusty, insert tons o
excuses here, but...


I'm struggling with how the initial condition semantics are working in
XST's (6.1) verilog synthesizer for inferred registers (target V2pro):

All this is being tested by compiling and viewing with a logic analyzer.

live_pulse is an input which goes high for a single clock cycle.  This
is a gross hack upstream, but I got that to work.

But given that, I'm having trouble defining initial conditions for
inferred registers.  I don't want to wrap everything in a big reset
statement that is unnecessary, given that I'm not going to port this
to an ASIC so I'm perfectly happy with assuming "all registers shalt
start at 0"

The sample code:

     reg live_lag, live_lag2, live_lag3, live_lag4;
     // synthesis attribute INIT of live_lag3 is "R"
     always @(posedge clk_0)
        begin
	 live_lag <= live_pulse;
         live_lag2 <= (live_pulse ? 1 : 0);
	 live_lag3 <= (live_pulse ? 1 : live_lag3);
	 live_lag4 <= (live_pulse ? 1 : live_lag4);
        end

live_lag and live_lag2, as expected, are the live_pulse delayed a
single clock cycle, with the correctly inferred initial condition of
starting at 0.

live_lag3 and live_lag4 however, the synthesis tool reports as "value
never changes" and replaces with a logic 1, even when a synthesis
attribute is set for live_lag3 saying that its initial state should be
R (reset to 0).

Of course, in XDL synthesis, the Verilog "initial" construct is
ignored, so I can't use that.

So the stupid question du jour:  How does one specify initial register
conditions for synthesized registers in XST?  

Or do I just have to directly instantiate registers to get the right
property?
-- 
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu

See
http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0082_10.html
(or the same thing at http://tinyurl.com/5mfwf ) for the information on
Initial Value support in Verilog2001.

"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message
news:csmo1v$2u4n$1@agate.berkeley.edu...
> OK.  I'm just braindead, my verilog is horribly rusty, insert tons o
> excuses here, but...
>
>
> I'm struggling with how the initial condition semantics are working in
> XST's (6.1) verilog synthesizer for inferred registers (target V2pro):
>
> All this is being tested by compiling and viewing with a logic analyzer.
>
> live_pulse is an input which goes high for a single clock cycle.  This
> is a gross hack upstream, but I got that to work.
>
> But given that, I'm having trouble defining initial conditions for
> inferred registers.  I don't want to wrap everything in a big reset
> statement that is unnecessary, given that I'm not going to port this
> to an ASIC so I'm perfectly happy with assuming "all registers shalt
> start at 0"
>
> The sample code:
>
>      reg live_lag, live_lag2, live_lag3, live_lag4;
>      // synthesis attribute INIT of live_lag3 is "R"
>      always @(posedge clk_0)
>         begin
> live_lag <= live_pulse;
>          live_lag2 <= (live_pulse ? 1 : 0);
> live_lag3 <= (live_pulse ? 1 : live_lag3);
> live_lag4 <= (live_pulse ? 1 : live_lag4);
>         end
>
> live_lag and live_lag2, as expected, are the live_pulse delayed a
> single clock cycle, with the correctly inferred initial condition of
> starting at 0.
>
> live_lag3 and live_lag4 however, the synthesis tool reports as "value
> never changes" and replaces with a logic 1, even when a synthesis
> attribute is set for live_lag3 saying that its initial state should be
> R (reset to 0).
>
> Of course, in XDL synthesis, the Verilog "initial" construct is
> ignored, so I can't use that.
>
> So the stupid question du jour:  How does one specify initial register
> conditions for synthesized registers in XST?
>
> Or do I just have to directly instantiate registers to get the right
> property?
> -- 
> Nicholas C. Weaver.  to reply email to "nweaver" at the domain
> icsi.berkeley.edu

In article <WIBHd.9$ML4.142@news-west.eli.net>,
John_H <johnhandwork@mail.com> wrote:
>See
>http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0082_10.html
>(or the same thing at http://tinyurl.com/5mfwf ) for the information on
>Initial Value support in Verilog2001.

Ahh, all so simple!  


-- 
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu

Just use an assignment when you define the reg.  Initial blocks are
ignored as for synthesis only.

HTH,

Mike

module test_reg ( clk_0, live_pulse, live_lag, live_lag2, live_lag3,
live_lag4 );

input live_pulse, clk_0;

output reg live_lag, live_lag2, live_lag3 = 1'b0, live_lag4 = 1'b0;

always @(posedge clk_0)
begin
live_lag <= live_pulse;
live_lag2 <= (live_pulse ? 1 : 0);
live_lag3 <= (live_pulse ? 1 : live_lag3);
live_lag4 <= (live_pulse ? 1 : live_lag4);
end

endmodule

Nicholas Weaver wrote:
> OK.  I'm just braindead, my verilog is horribly rusty, insert tons o
> excuses here, but...
>
>
> I'm struggling with how the initial condition semantics are working
in
> XST's (6.1) verilog synthesizer for inferred registers (target
V2pro):
>
> All this is being tested by compiling and viewing with a logic
analyzer.
>
> live_pulse is an input which goes high for a single clock cycle.
This
> is a gross hack upstream, but I got that to work.
>
> But given that, I'm having trouble defining initial conditions for
> inferred registers.  I don't want to wrap everything in a big reset
> statement that is unnecessary, given that I'm not going to port this
> to an ASIC so I'm perfectly happy with assuming "all registers shalt
> start at 0"
>
> The sample code:
>
>      reg live_lag, live_lag2, live_lag3, live_lag4;
>      // synthesis attribute INIT of live_lag3 is "R"
>      always @(posedge clk_0)
>         begin
> 	 live_lag <= live_pulse;
>          live_lag2 <= (live_pulse ? 1 : 0);
> 	 live_lag3 <= (live_pulse ? 1 : live_lag3);
> 	 live_lag4 <= (live_pulse ? 1 : live_lag4);
>         end
>
> live_lag and live_lag2, as expected, are the live_pulse delayed a
> single clock cycle, with the correctly inferred initial condition of
> starting at 0.
>
> live_lag3 and live_lag4 however, the synthesis tool reports as "value
> never changes" and replaces with a logic 1, even when a synthesis
> attribute is set for live_lag3 saying that its initial state should
be
> R (reset to 0).
>
> Of course, in XDL synthesis, the Verilog "initial" construct is
> ignored, so I can't use that.
>
> So the stupid question du jour:  How does one specify initial
register
> conditions for synthesized registers in XST?
>
> Or do I just have to directly instantiate registers to get the right
> property?
> --
> Nicholas C. Weaver.  to reply email to "nweaver" at the domain
> icsi.berkeley.edu

Nicholas Weaver wrote:
> OK.  I'm just braindead, my verilog is horribly rusty, insert tons o
> excuses here, but...
>
>
> I'm struggling with how the initial condition semantics are working
in
> XST's (6.1) verilog synthesizer for inferred registers (target
V2pro):
>
> All this is being tested by compiling and viewing with a logic
analyzer.
>
> live_pulse is an input which goes high for a single clock cycle.
This
> is a gross hack upstream, but I got that to work.
>
> But given that, I'm having trouble defining initial conditions for
> inferred registers.  I don't want to wrap everything in a big reset
> statement that is unnecessary, given that I'm not going to port this
> to an ASIC so I'm perfectly happy with assuming "all registers shalt
> start at 0"
>
> The sample code:
>
>      reg live_lag, live_lag2, live_lag3, live_lag4;
>      // synthesis attribute INIT of live_lag3 is "R"
>      always @(posedge clk_0)
>         begin
> 	 live_lag <= live_pulse;
>          live_lag2 <= (live_pulse ? 1 : 0);
> 	 live_lag3 <= (live_pulse ? 1 : live_lag3);
> 	 live_lag4 <= (live_pulse ? 1 : live_lag4);
>         end
>
> live_lag and live_lag2, as expected, are the live_pulse delayed a
> single clock cycle, with the correctly inferred initial condition of
> starting at 0.
>
> live_lag3 and live_lag4 however, the synthesis tool reports as "value
> never changes" and replaces with a logic 1, even when a synthesis
> attribute is set for live_lag3 saying that its initial state should
be
> R (reset to 0).
>
>From the Constraints Guide:
"It is illegal to attach INIT to a net or signal in FPGAs."

You could instantiate an FD for live_lag3 and live_lag4 and
apply the INIT constraint to each flop, or instantiate FDC
for each signal even though the clear input of the FDC is
set to 1'b0 it will come up low.

I generally add a clear input to my lower level modules and
a reset term in my clocked processes like:

module foo (live_pulse, clear, clk, live_lag);
input live_pulse, clear, clk;
output live_lag;
always @ (posedge clk or posedge clear)
if (clear) live_lag <= 0;
else live_lag <= live_pulse ? 1 : live_lag;
endmodule

Then at the upper level I tie the module's clear input to 1'b0,
which is like what happens with the FDC.  The clear doesn't
create hardware, it just forces the proper initial state after
loading.

For 1 or 2 signals at the top level, instantiating the FDC is
usually easier.  By the way does the synthesis also rip out
your signals if you code them like this?
if (live_pulse) live_lag3 <= 1;

> Of course, in XDL synthesis, the Verilog "initial" construct is
> ignored, so I can't use that.
>
> So the stupid question du jour:  How does one specify initial
register
> conditions for synthesized registers in XST?
>
> Or do I just have to directly instantiate registers to get the right
> property?
> --
> Nicholas C. Weaver.  to reply email to "nweaver" at the domain
> icsi.berkeley.edu