Is a gated oscillator using NAND okay within a Cyclone FPGA?

Hello,

I'm brand new to the world of FPGA's and would like to know if I can
implement a gated oscillator using a NAND gate (the output tied back to
one of the inputs, and the other input as the gate) within my Cyclone I
device?

Thanks for the newbie help!

Len G

This is not an Altera vs Xilinx issue. It has the same problem and
solution in any logic circuit:

1. This oscillator will be outrageously fast, unless you insert
additional delay in the feedback path.

2. when you turn the oscillator off (by pulling the NAND input Low) you
will abruptly force the output High. That might generate a "runt" clock
pulse if the output was Low.
Solution: insert a flip-flop such that its Q drives the NAND control
input. Use the D input connected to the asynchronous (active High)
Preset of this flip-flop as the oscillator enable input. The flip-flop
must be clocked on the rising clock edge.
De-activating the oscillator will now occur right after the clock has
gone High.
Peter Alfke, Xilinx Applications

Hi Peter,

I didn't mean to infer any kind of Xilinx/Altera issue or comparison,
just wanted to say which one I was using.  Thanks for the flip flop
input.  When using discrete logic, I get a clock of about 1.65 MHz, but
don't know what it would come out to inside the FPGA.  (obviously I
need to practice with some real hardware sometime REAL SOON  ;)  

Len

Len wrote:
> Hello,
>
> I'm brand new to the world of FPGA's and would like to know if I can
> implement a gated oscillator using a NAND gate (the output tied back
to
> one of the inputs, and the other input as the gate) within my Cyclone
I
> device?
>
> Thanks for the newbie help!
>
> Len G

Hi Len,

You probably won't like my answer: Don't do it. Sure, you can create a
circuit that behaves that way (I would call it a glitch generator
rather than an oscillator!) but there are pitfalls: you might 'tune'
the circuit to work on one FPGA and then recompile for a different
device family and suddenly have different timing, or change a
synthesis/fitting option and get a different result. In summary it can
certainly be done, but in general it is not a reccomended design
practice, at least in how I learned to do things.

Would it be possible just to use a built-in PLL instead to get the
clock you exactly want?

Jesse Kempa
Altera
jkempa at altera dot com

Hi Jesse,

Well, I think it would be easier to - at least take my glitch generator
out of the chip!  I'm just trying to generate a clock that I can gate
with Horizontal sync.  I would then feed the clock to a
counter/comparator to be used to set horizontal position for a title. I
sort of had worries about doing it this way, so will just take the
noise and go "outside".  A CD4093 gives me a nice (slower) clock
frequency to use, and since it's gated on every Horiz line, it stays
quite stable.   I don't have much experience w/ PLL's, so think I'd
better keep it simple, at least for now.

Do you mind if I send you an email at altera.com?

Thanks,
Len

Hi, Len.
If you dislike external ICs, you can make any FPGA (or CPLD) implement
a very stable and reliable oscillator, using two external resistors +
one C. Click on
http://www.xilinx.com/xlnx/xweb/xil_tx_home.jsp
and look for "Six easy pieces #3" by yours truly.
It's always a safe bet to warn against asynchronous and analog circuit
tricks, but sometimes they are the only way out of a bind...
But these tricks do require a good understanding of circuitry, not just
VHDL or Verilog.
Peter Alfke, Xilinx (from home)

"Len" <LeonardGabrielson@adelphia.net> schrieb im Newsbeitrag
news:1116286221.349685.128570@f14g2000cwb.googlegroups.com...
> Hi Peter,
>
> I didn't mean to infer any kind of Xilinx/Altera issue or comparison,
> just wanted to say which one I was using.  Thanks for the flip flop
> input.  When using discrete logic, I get a clock of about 1.65 MHz, but
> don't know what it would come out to inside the FPGA.  (obviously I
> need to practice with some real hardware sometime REAL SOON  ;)
>
> Len
>

the PLD or FPGA implementation would run way faster. But you can tailor it
to your need to using different resources. A gated osc on XC9500XL that uses
IOPAD (but no external components) runs above 40MHz. So thumb rule. A small
immersed in FPGA fabric ring oscillator would run way faster. as said
already the actual frequency is very dependand on the mapping and routing
(speciall in FPGA!) so you should make a 'hard macro' and lock it down if
you somewhat repeatable frequency. Another approuch would be to make a ring
oscillator that runs as fast as it cans and you have an NCO circuit that is
calibrated with correct coefficent to produce the clock you need

antti

Use the Horizontal sync as enable to your counter and feed the dot clk 
to the counter
Aurash
Len wrote:

>Hi Jesse,
>
>Well, I think it would be easier to - at least take my glitch generator
>out of the chip!  I'm just trying to generate a clock that I can gate
>with Horizontal sync.  I would then feed the clock to a
>counter/comparator to be used to set horizontal position for a title. I
>sort of had worries about doing it this way, so will just take the
>noise and go "outside".  A CD4093 gives me a nice (slower) clock
>frequency to use, and since it's gated on every Horiz line, it stays
>quite stable.   I don't have much experience w/ PLL's, so think I'd
>better keep it simple, at least for now.
>
>Do you mind if I send you an email at altera.com?
>
>Thanks,
>Len
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Hi Peter,

Peter Alfke wrote:
> Click on
> http://www.xilinx.com/xlnx/xweb/xil_tx_home.jsp
> and look for "Six easy pieces #3" by yours truly.

Just read them, and they turned out very helpfull for the tinkering I'm 
doing. Thanks for sharing! Any plans on 'Six not so easy pieces"?

Regards, Paul Boven.