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JTAG port access in Cyclone

Started by Jedi June 21, 2005
Jedi, Antti,

Unfortunately the only official support of this nature is to allow your
FPGA logic to access the SPI config port (rather than your host PC
doing this). This is done by using either the EPCS serial flash
controller or ASMI memory interface peripherals in SOPC Builder. Create
an Avalon interface from your design to drive the peripheral you use
and proceed from there.

Access to extending the JTAG chain in the device and driving these from
the host PC are, at least for now, proprietary.

Jesse Kempa
Altera
jkempa -at- altera -dot- com

<kempaj@yahoo.com> schrieb im Newsbeitrag
news:1119456961.738656.316600@g14g2000cwa.googlegroups.com...
> Jedi, Antti, > > Unfortunately the only official support of this nature is to allow your > FPGA logic to access the SPI config port (rather than your host PC > doing this). This is done by using either the EPCS serial flash > controller or ASMI memory interface peripherals in SOPC Builder. Create > an Avalon interface from your design to drive the peripheral you use > and proceed from there. > > Access to extending the JTAG chain in the device and driving these from > the host PC are, at least for now, proprietary. > > Jesse Kempa > Altera > jkempa -at- altera -dot- com >
ok, at least we now know 'what is official' - To Altera - the ASMI and JTAG scan primitive has been used by different people outside the 'official' scope, partially by doing some RE on subject as the official documents hide some information about such useage. hiding some features from the customers is not a good idea, IMHO. Actually I feel its rather stupid thing todo. You cant hide whats already partially visible. Any such info hiding attempts just make people pissed off. And it would not stay hidden anyway, nothing ever has. most of the info to access JTAG primitive is there http://wiki.openchip.org/index.php/Altera:JTAG ASMI direct useage without SOPC has been documented also several times by non-altera 3rd parties. Antti
Antti Lukats wrote:
> <kempaj@yahoo.com> schrieb im Newsbeitrag > news:1119456961.738656.316600@g14g2000cwa.googlegroups.com... > >>Jedi, Antti, >> >>Unfortunately the only official support of this nature is to allow your >>FPGA logic to access the SPI config port (rather than your host PC >>doing this). This is done by using either the EPCS serial flash >>controller or ASMI memory interface peripherals in SOPC Builder. Create >>an Avalon interface from your design to drive the peripheral you use >>and proceed from there. >> >>Access to extending the JTAG chain in the device and driving these from >>the host PC are, at least for now, proprietary. >> >>Jesse Kempa >>Altera >>jkempa -at- altera -dot- com >> > > > ok, at least we now know 'what is official' - > > To Altera - the ASMI and JTAG scan primitive has been used by different > people outside the 'official' scope, partially by doing some RE on subject > as the official documents hide some information about such useage. > > hiding some features from the customers is not a good idea, IMHO. Actually I > feel its rather stupid thing todo. You cant hide whats already partially > visible. Any such info hiding attempts just make people pissed off. And it > would not stay hidden anyway, nothing ever has. > > most of the info to access JTAG primitive is there > > http://wiki.openchip.org/index.php/Altera:JTAG > > ASMI direct useage without SOPC has been documented also several times by > non-altera 3rd parties. >
To: whom it may concern Not only ASMI usage but also EPCS replacement has been documented and tested with several vendors. One vendors already did it by himself...I can post his repliy here if anybody wants (o; I rather see it as a great feature and "kuul" making stuff like USER JTAG available and documented...doesn't it give some advantage over other vendors? Speaking of hiding I don't really see also the point in removing the NIOS toolchain sources from ftp server, as done some 2 or 3 weeks ago...well...they were obsolete and software developers doing work on BSD systems don't have any chance to use the eval versions toolchain (o; rick