Implement a JTAG controller in an FPGA

Anyone done a JTAG controller in VHDL or Verilog?

I want to use an FPGA to program another JTAG device.

Cheers,

Irish

"irish" <decalternate@hotmail.com> schrieb im Newsbeitrag
news:1121267183.940988.167760@o13g2000cwo.googlegroups.com...
> Anyone done a JTAG controller in VHDL or Verilog?
>
> I want to use an FPGA to program another JTAG device.
>
> Cheers,
>
> Irish

sure, but well its 'application dependant' in most cases.

if you have a softcore cpu, then TAP master is in simplest form 4 bit wide
GPIO port and all the rest is software.

without specifics its not possible to help you to choose the solution

some sort of TAP master is in somewhere in product support zip files in the
www.mesanet.com but its not useable standalone, and when you already have a
procesor and speed is not so critical you can just use bit bang GPIO, so
there would be no need for the TAP master in hardware

Antti

As far as I remember, Lattice has a reference design on multiple
boundary scan port linker, see
http://www.latticesemi.com/products/devtools/ip/refdesigns/index.cfm

I think this can be used to program other devices through one
centralised device. Please correct me if I'm wrong.

Luc

On 13 Jul 2005 08:06:24 -0700, "irish" <decalternate@hotmail.com>
wrote:

>Anyone done a JTAG controller in VHDL or Verilog?
>
>I want to use an FPGA to program another JTAG device.
>
>Cheers,
>
>Irish

"Luc" <lb.edc@pandora.be> schrieb im Newsbeitrag
news:a0uad1psrtooqcvemivkqrbu3hh3svv5e5@4ax.com...
> As far as I remember, Lattice has a reference design on multiple
> boundary scan port linker, see
> http://www.latticesemi.com/products/devtools/ip/refdesigns/index.cfm
>
> I think this can be used to program other devices through one
> centralised device. Please correct me if I'm wrong.
>
> Luc
>
> On 13 Jul 2005 08:06:24 -0700, "irish" <decalternate@hotmail.com>
> wrote:
>
> >Anyone done a JTAG controller in VHDL or Verilog?
> >
> >I want to use an FPGA to program another JTAG device.
> >
> >Cheers,
> >
> >Irish
>

there are only JEDEC files for the those boundary scan linker designs, not
much useful at all

and I think OP was not looking for this type of thing but TAP master

Antti