Simple system to manage register access in hierarchical Wishbone-connected FPGA designs.

Hi,

I needed to provide convenient access to registers in an FPGA design internally interconnected with Wishbone/IPbus bus. There is a wonderful tool - wbgen2 in the OHWR directory, but it doesn't support nested slaves neither vectors of registers. Therefore, I've decided to prepare a similar tool, based on wbgen2 concept, but written in Python.
The first version is already available in https://github.com/wzab/addr_gen_wb
and is available under GPL v2 license.
The solution is oriented on control applications not on high-traffic data transfer. Therefore, it supports onle classic mode single accesses.
Please note, that the code was written just in a few days, so it is not well structured. However, I hope that it may be usefull for others. I'll appreciate any remarks, suggestions of improvements or bug fixes.

With best regards,
Wojtek