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Virtex 2 configuration problem

Started by gja January 4, 2006
I'm looking for some suggestions as to what else to look at to fix this 
problem:

Using a Virtex II xc2v40 and xcf02s prom connected in master serial mode. 
JTAG is also implemented.  We've built around 50 of these boards without 
this problem so I believe it's just this particular board.  It 
intermittently doesn't configure on power up.

A power chip holds INIT_B low until 3.3v is 3v to delay configuration, not 
really needed since power ramps up in around 5ms.  When it fails, I see on a 
scope that INIT_B never goes high after power is up and PROG is high. PROG 
is pulled up to 3.3v thru 4.75k. When it works, INIT_B goes high within 5ms 
of PROG going high.

As a test, I connected PROG to GND with a wire and then powered up the 
board. After say 5 secs, I disconnected GND, and sometimes  INIT_B would go 
high as expected, But sometimes it would remain low. If it went high, I 
could pulse PROG low and INIT_B would work as expected everytime.

When the fpga is in its nonworking state, it doesn't respond on the JTAG 
port either.

I lifted the prom pin and the power chip connected to INIT_B to verify that 
when it fails, it's the fpga that is holding INIT_B low and not the other 
chips.

Any ideas on what else to look at? 


"gja" <gja@hotmail.com> schrieb im Newsbeitrag 
news:nq%uf.3818$DY3.3339@fe09.lga...
> I'm looking for some suggestions as to what else to look at to fix this > problem: > > Using a Virtex II xc2v40 and xcf02s prom connected in master serial mode. > JTAG is also implemented. We've built around 50 of these boards without > this problem so I believe it's just this particular board. It > intermittently doesn't configure on power up. > > A power chip holds INIT_B low until 3.3v is 3v to delay configuration, not > really needed since power ramps up in around 5ms. When it fails, I see on > a scope that INIT_B never goes high after power is up and PROG is high. > PROG is pulled up to 3.3v thru 4.75k. When it works, INIT_B goes high > within 5ms of PROG going high. > > As a test, I connected PROG to GND with a wire and then powered up the > board. After say 5 secs, I disconnected GND, and sometimes INIT_B would > go high as expected, But sometimes it would remain low. If it went high, I > could pulse PROG low and INIT_B would work as expected everytime. > > When the fpga is in its nonworking state, it doesn't respond on the JTAG > port either. > > I lifted the prom pin and the power chip connected to INIT_B to verify > that when it fails, it's the fpga that is holding INIT_B low and not the > other chips. > > Any ideas on what else to look at? >
if INIT_B does not go high there isnt much too look at - init output and its corresponding bit in IR capture readback and in configuration status register does indicate "internal housecleaning complete" if it remains Low then FPGA is basic internal failure mode only power supply and PROG_B can possible prevent the INIT_B from going low (or malfunctionining FPGA) if JTAG works at all you can check the init_b bit in IR capture, if JTAG doesnt work at all, then I assume bad FPGA or bad power supply -- Antti Lukats http://www.xilant.com
"Antti Lukats" <antti@openchip.org> wrote in message
news:dpigr1$dms$01$1@news.t-online.com...
> "gja" <gja@hotmail.com> schrieb im Newsbeitrag > news:nq%uf.3818$DY3.3339@fe09.lga... > > I'm looking for some suggestions as to what else to look at to fix this > > problem: > > > > Using a Virtex II xc2v40 and xcf02s prom connected in master serial
mode.
> > JTAG is also implemented. We've built around 50 of these boards without > > this problem so I believe it's just this particular board. It > > intermittently doesn't configure on power up. > > > > A power chip holds INIT_B low until 3.3v is 3v to delay configuration,
not
> > really needed since power ramps up in around 5ms. When it fails, I see
on
> > a scope that INIT_B never goes high after power is up and PROG is high. > > PROG is pulled up to 3.3v thru 4.75k. When it works, INIT_B goes high > > within 5ms of PROG going high. > > > > As a test, I connected PROG to GND with a wire and then powered up the > > board. After say 5 secs, I disconnected GND, and sometimes INIT_B would > > go high as expected, But sometimes it would remain low. If it went high,
I
> > could pulse PROG low and INIT_B would work as expected everytime. > > > > When the fpga is in its nonworking state, it doesn't respond on the JTAG > > port either. > > > > I lifted the prom pin and the power chip connected to INIT_B to verify > > that when it fails, it's the fpga that is holding INIT_B low and not the > > other chips. > > > > Any ideas on what else to look at? > > > if INIT_B does not go high there isnt much too look at - init output and
its
> corresponding bit in IR capture readback and in configuration status > register does indicate "internal housecleaning complete" if it remains Low > then FPGA is basic internal failure mode > > only power supply and PROG_B can possible prevent the INIT_B from going
low
> (or malfunctionining FPGA) > > if JTAG works at all you can check the init_b bit in IR capture, if JTAG > doesnt work at all, then I assume bad FPGA or bad power supply > > -- > Antti Lukats > http://www.xilant.com > >
Do you think it's a fair test to gnd the PROG_B signal and release it about 10secs after power is on? Holding PROG_B low basically holds off configuration also? Does that negate the powerup requirements?